[llvm] [AArch64] Drop poison flags when lowering absolute difference patterns. (PR #152130)

[Ricardo Jesus via llvm-commits]

https://github.com/rj-jesus created https://github.com/llvm/llvm-project/pull/152130

As a follow-up to #151177, when lowering SELECT_CC nodes of absolute difference patterns, drop poison-generating flags from the negated operand to avoid inadvertently propagating poison.

As discussed in https://github.com/llvm/llvm-project/pull/151177#discussion_r2250788112, I didn't find practical issues with the current code, but it seems safer to drop flags preemptively.

I don't know of a good way to test this other than by matching SDAG logs directly.

>From cb2cc626e77dba6d5c4b35e1770b3b33b55181e3 Mon Sep 17 00:00:00 2001
From: Ricardo Jesus <rjj at nvidia.com>
Date: Mon, 4 Aug 2025 02:14:54 -0700
Subject: [PATCH] [AArch64] Drop poison flags when lowering absolute difference
 patterns.

When lowering SELECT_CC nodes of absolute difference patterns, drop
poison generating flags from the negated operand to avoid inadvertently
propagating poison.
---
 llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 4f6e3ddd18def..c1cff5b8431a8 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -11398,13 +11398,18 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(
     //   select_cc lhs, rhs, sub(rhs, lhs), sub(lhs, rhs), cc ->
     //   select_cc lhs, rhs, neg(sub(lhs, rhs)), sub(lhs, rhs), cc
     // The second forms can be matched into subs+cneg.
+    // NOTE: Drop poison generating flags from the negated operand to avoid
+    // inadvertently propagating poison after the canonicalisation.
     if (TVal.getOpcode() == ISD::SUB && FVal.getOpcode() == ISD::SUB) {
       if (TVal.getOperand(0) == LHS && TVal.getOperand(1) == RHS &&
-          FVal.getOperand(0) == RHS && FVal.getOperand(1) == LHS)
+          FVal.getOperand(0) == RHS && FVal.getOperand(1) == LHS) {
         FVal = DAG.getNegative(TVal, DL, TVal.getValueType());
-      else if (TVal.getOperand(0) == RHS && TVal.getOperand(1) == LHS &&
-               FVal.getOperand(0) == LHS && FVal.getOperand(1) == RHS)
+        TVal->dropFlags(SDNodeFlags::PoisonGeneratingFlags);
+      } else if (TVal.getOperand(0) == RHS && TVal.getOperand(1) == LHS &&
+                 FVal.getOperand(0) == LHS && FVal.getOperand(1) == RHS) {
         TVal = DAG.getNegative(FVal, DL, FVal.getValueType());
+        FVal->dropFlags(SDNodeFlags::PoisonGeneratingFlags);
+      }
     }
 
     unsigned Opcode = AArch64ISD::CSEL;