[llvm] [AArch64] Support MI and PL (PR #150314)

[David Green via llvm-commits]

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@@ -3320,7 +3320,8 @@ static bool isZerosVector(const SDNode *N) {
 
 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
 /// CC
-static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
+static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC, SDValue RHS,
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davemgreen wrote:

Could this use SDValue RHS = {} to not require canUsePLOrMI?

https://github.com/llvm/llvm-project/pull/150314