[lldb] [llvm] Annotate disassembly with register‐resident variable locations (PR #147460)

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``````````bash
darker --check --diff -r HEAD~1...HEAD lldb/test/API/functionalities/rich-disassembler/TestRichDisassembler.py
``````````

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``````````diff
--- TestRichDisassembler.py	2025-08-04 19:52:18.000000 +0000
+++ TestRichDisassembler.py	2025-08-04 19:55:45.118163 +0000
@@ -1,17 +1,17 @@
 from lldbsuite.test.lldbtest import *
 from lldbsuite.test.decorators import *
+
 
 class TestRichDisassembler(TestBase):
     def test_d_original_example_O1(self):
         """
         Tests disassembler output for d_original_example.c built with -O1.
         """
-        self.build(dictionary={
-            'C_SOURCES': 'd_original_example.c',
-            'CFLAGS_EXTRAS': '-g -O1'
-        })
+        self.build(
+            dictionary={"C_SOURCES": "d_original_example.c", "CFLAGS_EXTRAS": "-g -O1"}
+        )
         exe = self.getBuildArtifact("a.out")
         target = self.dbg.CreateTarget(exe)
         self.assertTrue(target)
 
         breakpoint = target.BreakpointCreateByName("main")
@@ -29,15 +29,5 @@
         self.assertIn("argv = ", disasm)
         self.assertIn("i = ", disasm)
         # self.assertIn("DW_OP_reg", disasm)
         # self.assertIn("DW_OP_stack_value", disasm)
         self.assertNotIn("<decoding error>", disasm)
-
-
-    
-
-
-
-
-
-
-

``````````

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https://github.com/llvm/llvm-project/pull/147460