[llvm] [ARM] Have custom lowering for ucmp and scmp (PR #149315)

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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp,h -- llvm/lib/Target/ARM/ARMISelLowering.cpp llvm/lib/Target/ARM/ARMISelLowering.h
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<details>
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 53a25d633..ab7cd4782 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -10627,8 +10627,9 @@ SDValue ARMTargetLowering::LowerFP_TO_BF16(SDValue Op,
   return DAG.getBitcast(MVT::i32, Res);
 }
 
-SDValue ARMTargetLowering::LowerCMP_COMMON(SDValue Op, SelectionDAG &DAG, 
-                                           ARMCC::CondCodes GTCond, ARMCC::CondCodes LTCond, 
+SDValue ARMTargetLowering::LowerCMP_COMMON(SDValue Op, SelectionDAG &DAG,
+                                           ARMCC::CondCodes GTCond,
+                                           ARMCC::CondCodes LTCond,
                                            bool IsSigned) const {
   SDLoc dl(Op);
   SDValue LHS = Op.getOperand(0);
@@ -10663,7 +10664,8 @@ SDValue ARMTargetLowering::LowerCMP_COMMON(SDValue Op, SelectionDAG &DAG,
 
       if (CanUseAdd) {
         Opcode = ARMISD::ADDC;
-        AddOperand = SubRHS; // Replace RHS with X, so we do LHS + X instead of LHS - (0 - X)
+        AddOperand = SubRHS; // Replace RHS with X, so we do LHS + X instead of
+                             // LHS - (0 - X)
       }
     }
   }
@@ -10672,10 +10674,12 @@ SDValue ARMTargetLowering::LowerCMP_COMMON(SDValue Op, SelectionDAG &DAG,
   SDValue OpWithFlags;
   if (Opcode == ARMISD::ADDC) {
     // Use ADDC: LHS + AddOperand (where RHS was 0 - AddOperand)
-    OpWithFlags = DAG.getNode(ARMISD::ADDC, dl, DAG.getVTList(MVT::i32, FlagsVT), LHS, AddOperand);
+    OpWithFlags = DAG.getNode(
+        ARMISD::ADDC, dl, DAG.getVTList(MVT::i32, FlagsVT), LHS, AddOperand);
   } else {
     // Use ARMISD::SUBC to generate SUBS instruction (subtract with flags)
-    OpWithFlags = DAG.getNode(ARMISD::SUBC, dl, DAG.getVTList(MVT::i32, FlagsVT), LHS, RHS);
+    OpWithFlags = DAG.getNode(ARMISD::SUBC, dl,
+                              DAG.getVTList(MVT::i32, FlagsVT), LHS, RHS);
   }
 
   SDValue OpResult = OpWithFlags.getValue(0); // The operation result
@@ -10687,13 +10691,13 @@ SDValue ARMTargetLowering::LowerCMP_COMMON(SDValue Op, SelectionDAG &DAG,
 
   // First conditional move: if greater than, set to 1
   SDValue GTCondValue = DAG.getConstant(GTCond, dl, MVT::i32);
-  SDValue Result1 =
-      DAG.getNode(ARMISD::CMOV, dl, MVT::i32, OpResult, One, GTCondValue, Flags);
+  SDValue Result1 = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, OpResult, One,
+                                GTCondValue, Flags);
 
   // Second conditional move: if less than, set to -1
   SDValue LTCondValue = DAG.getConstant(LTCond, dl, MVT::i32);
-  SDValue Result2 =
-      DAG.getNode(ARMISD::CMOV, dl, MVT::i32, Result1, MinusOne, LTCondValue, Flags);
+  SDValue Result2 = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, Result1, MinusOne,
+                                LTCondValue, Flags);
 
   if (Op.getValueType() != MVT::i32)
     Result2 = DAG.getSExtOrTrunc(Result2, dl, Op.getValueType());
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
index 70db2eaf1..d48017a53 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -908,7 +908,9 @@ class VectorType;
     SDValue LowerFP_TO_BF16(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerSCMP(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerUCMP(SDValue Op, SelectionDAG &DAG) const;
-    SDValue LowerCMP_COMMON(SDValue Op, SelectionDAG &DAG, ARMCC::CondCodes GTCond, ARMCC::CondCodes LTCond, bool IsSigned) const;
+    SDValue LowerCMP_COMMON(SDValue Op, SelectionDAG &DAG,
+                            ARMCC::CondCodes GTCond, ARMCC::CondCodes LTCond,
+                            bool IsSigned) const;
 
     Register getRegisterByName(const char* RegName, LLT VT,
                                const MachineFunction &MF) const override;

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https://github.com/llvm/llvm-project/pull/149315