[llvm] [NFC] [PowerPC] Auto-generate check-zero-vector.ll (PR #151991)
Guy David via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 4 08:47:02 PDT 2025
https://github.com/guy-david created https://github.com/llvm/llvm-project/pull/151991
Should make it easier to update the test and highlight the diff against incoming patches, as seen in this PR: https://github.com/llvm/llvm-project/pull/146806.
>From 5d6d051eb61c23aaab94add7d91a788afd11bb62 Mon Sep 17 00:00:00 2001
From: Guy David <guyda96 at gmail.com>
Date: Mon, 4 Aug 2025 18:41:40 +0300
Subject: [PATCH] [NFC] [PowerPC] Auto-generate check-zero-vector.ll
Should make it easier to update the test and highlight the diff against
incoming patches.
---
.../test/CodeGen/PowerPC/check-zero-vector.ll | 698 ++++++++++++++++--
1 file changed, 625 insertions(+), 73 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/check-zero-vector.ll b/llvm/test/CodeGen/PowerPC/check-zero-vector.ll
index 59173e22edf26..e6367e65d7200 100644
--- a/llvm/test/CodeGen/PowerPC/check-zero-vector.ll
+++ b/llvm/test/CodeGen/PowerPC/check-zero-vector.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: < %s | FileCheck %s --check-prefix=POWERPC_64LE
@@ -10,96 +11,647 @@
define i32 @test_Greater_than(ptr %colauths, i32 signext %ncols) {
; This testcase is manually reduced to isolate the critical code blocks.
; It is designed to check for vector comparison specifically for zero vectors.
-; In the vector.body section, we are expecting a comparison instruction (vcmpequh),
-; merge instructions (vmrghh and vmrglh) which use exactly 2 vectors.
-; The output of the merge instruction is being used by xxland and finally
+; In the vector.body section, we are expecting a comparison instruction (vcmpequh),
+; merge instructions (vmrghh and vmrglh) which use exactly 2 vectors.
+; The output of the merge instruction is being used by xxland and finally
; accumulated by vadduwm instruction.
-
; POWERPC_64LE-LABEL: test_Greater_than:
-; POWERPC_64LE: .LBB0_6: # %vector.body
+; POWERPC_64LE: # %bb.0: # %entry
+; POWERPC_64LE-NEXT: cmpwi 4, 0
+; POWERPC_64LE-NEXT: ble 0, .LBB0_3
+; POWERPC_64LE-NEXT: # %bb.1: # %iter.check
+; POWERPC_64LE-NEXT: clrldi 5, 4, 32
+; POWERPC_64LE-NEXT: cmplwi 4, 7
+; POWERPC_64LE-NEXT: bgt 0, .LBB0_4
+; POWERPC_64LE-NEXT: # %bb.2:
+; POWERPC_64LE-NEXT: li 4, 0
+; POWERPC_64LE-NEXT: li 6, 0
+; POWERPC_64LE-NEXT: b .LBB0_12
+; POWERPC_64LE-NEXT: .LBB0_3:
+; POWERPC_64LE-NEXT: li 4, 0
+; POWERPC_64LE-NEXT: mr 3, 4
+; POWERPC_64LE-NEXT: blr
+; POWERPC_64LE-NEXT: .LBB0_4: # %vector.main.loop.iter.check
+; POWERPC_64LE-NEXT: vspltisw 2, 1
+; POWERPC_64LE-NEXT: li 7, 0
+; POWERPC_64LE-NEXT: li 6, 0
+; POWERPC_64LE-NEXT: cmplwi 4, 64
+; POWERPC_64LE-NEXT: li 4, 0
+; POWERPC_64LE-NEXT: blt 0, .LBB0_9
+; POWERPC_64LE-NEXT: # %bb.5: # %vector.ph
+; POWERPC_64LE-NEXT: rlwinm 6, 5, 0, 1, 25
+; POWERPC_64LE-NEXT: addi 4, 3, 64
+; POWERPC_64LE-NEXT: xxlxor 35, 35, 35
+; POWERPC_64LE-NEXT: addi 8, 6, -64
+; POWERPC_64LE-NEXT: xxlxor 36, 36, 36
+; POWERPC_64LE-NEXT: rldicl 8, 8, 58, 6
+; POWERPC_64LE-NEXT: xxlxor 37, 37, 37
+; POWERPC_64LE-NEXT: xxlxor 32, 32, 32
+; POWERPC_64LE-NEXT: xxlxor 39, 39, 39
+; POWERPC_64LE-NEXT: xxlxor 33, 33, 33
+; POWERPC_64LE-NEXT: xxlxor 42, 42, 42
+; POWERPC_64LE-NEXT: xxlxor 40, 40, 40
+; POWERPC_64LE-NEXT: addi 8, 8, 1
+; POWERPC_64LE-NEXT: xxlxor 41, 41, 41
+; POWERPC_64LE-NEXT: mtctr 8
+; POWERPC_64LE-NEXT: xxlxor 38, 38, 38
+; POWERPC_64LE-NEXT: xxlxor 46, 46, 46
+; POWERPC_64LE-NEXT: xxlxor 43, 43, 43
+; POWERPC_64LE-NEXT: xxlxor 44, 44, 44
+; POWERPC_64LE-NEXT: xxlxor 45, 45, 45
+; POWERPC_64LE-NEXT: xxlxor 49, 49, 49
+; POWERPC_64LE-NEXT: xxlxor 47, 47, 47
+; POWERPC_64LE-NEXT: xxlxor 48, 48, 48
+; POWERPC_64LE-NEXT: .p2align 4
+; POWERPC_64LE-NEXT: .LBB0_6: # %vector.body
; POWERPC_64LE-NEXT: #
-; POWERPC_64LE-NEXT: lxv [[R1:[0-9]+]], -64(4)
-; POWERPC_64LE-NEXT: vcmpequh [[R2:[0-9]+]], [[R2]], [[R3:[0-9]+]]
-; POWERPC_64LE-NEXT: xxlnor [[R1]], [[R1]], [[R1]]
-; POWERPC_64LE-NEXT: vmrghh [[R4:[0-9]+]], [[R2]], [[R2]]
-; POWERPC_64LE-NEXT: vmrglh [[R2]], [[R2]], [[R2]]
-; POWERPC_64LE-NEXT: xxland [[R5:[0-9]+]], [[R5]], [[R6:[0-9]+]]
-; POWERPC_64LE-NEXT: xxland [[R1]], [[R1]], [[R6]]
-; POWERPC_64LE-NEXT: vadduwm [[R7:[0-9]+]], [[R7]], [[R4]]
-; POWERPC_64LE: .LBB0_10: # %vec.epilog.vector.body
+; POWERPC_64LE-NEXT: lxv 50, -64(4)
+; POWERPC_64LE-NEXT: vcmpequh 18, 18, 3
+; POWERPC_64LE-NEXT: xxlnor 50, 50, 50
+; POWERPC_64LE-NEXT: vmrghh 19, 18, 18
+; POWERPC_64LE-NEXT: vmrglh 18, 18, 18
+; POWERPC_64LE-NEXT: xxland 51, 51, 34
+; POWERPC_64LE-NEXT: xxland 50, 50, 34
+; POWERPC_64LE-NEXT: vadduwm 5, 5, 19
+; POWERPC_64LE-NEXT: lxv 51, -48(4)
+; POWERPC_64LE-NEXT: vadduwm 4, 4, 18
+; POWERPC_64LE-NEXT: vcmpequh 19, 19, 3
+; POWERPC_64LE-NEXT: xxlnor 51, 51, 51
+; POWERPC_64LE-NEXT: vmrghh 18, 19, 19
+; POWERPC_64LE-NEXT: vmrglh 19, 19, 19
+; POWERPC_64LE-NEXT: xxland 50, 50, 34
+; POWERPC_64LE-NEXT: xxland 51, 51, 34
+; POWERPC_64LE-NEXT: vadduwm 7, 7, 18
+; POWERPC_64LE-NEXT: lxv 50, -32(4)
+; POWERPC_64LE-NEXT: vadduwm 0, 0, 19
+; POWERPC_64LE-NEXT: vcmpequh 18, 18, 3
+; POWERPC_64LE-NEXT: xxlnor 50, 50, 50
+; POWERPC_64LE-NEXT: vmrghh 19, 18, 18
+; POWERPC_64LE-NEXT: vmrglh 18, 18, 18
+; POWERPC_64LE-NEXT: xxland 51, 51, 34
+; POWERPC_64LE-NEXT: xxland 50, 50, 34
+; POWERPC_64LE-NEXT: vadduwm 10, 10, 19
+; POWERPC_64LE-NEXT: lxv 51, -16(4)
+; POWERPC_64LE-NEXT: vadduwm 1, 1, 18
+; POWERPC_64LE-NEXT: vcmpequh 19, 19, 3
+; POWERPC_64LE-NEXT: xxlnor 51, 51, 51
+; POWERPC_64LE-NEXT: vmrghh 18, 19, 19
+; POWERPC_64LE-NEXT: vmrglh 19, 19, 19
+; POWERPC_64LE-NEXT: xxland 50, 50, 34
+; POWERPC_64LE-NEXT: xxland 51, 51, 34
+; POWERPC_64LE-NEXT: vadduwm 9, 9, 18
+; POWERPC_64LE-NEXT: lxv 50, 0(4)
+; POWERPC_64LE-NEXT: vadduwm 8, 8, 19
+; POWERPC_64LE-NEXT: vcmpequh 18, 18, 3
+; POWERPC_64LE-NEXT: xxlnor 50, 50, 50
+; POWERPC_64LE-NEXT: vmrghh 19, 18, 18
+; POWERPC_64LE-NEXT: vmrglh 18, 18, 18
+; POWERPC_64LE-NEXT: xxland 51, 51, 34
+; POWERPC_64LE-NEXT: xxland 50, 50, 34
+; POWERPC_64LE-NEXT: vadduwm 14, 14, 19
+; POWERPC_64LE-NEXT: lxv 51, 16(4)
+; POWERPC_64LE-NEXT: vadduwm 6, 6, 18
+; POWERPC_64LE-NEXT: vcmpequh 19, 19, 3
+; POWERPC_64LE-NEXT: xxlnor 51, 51, 51
+; POWERPC_64LE-NEXT: vmrghh 18, 19, 19
+; POWERPC_64LE-NEXT: vmrglh 19, 19, 19
+; POWERPC_64LE-NEXT: xxland 50, 50, 34
+; POWERPC_64LE-NEXT: xxland 51, 51, 34
+; POWERPC_64LE-NEXT: vadduwm 12, 12, 18
+; POWERPC_64LE-NEXT: lxv 50, 32(4)
+; POWERPC_64LE-NEXT: vadduwm 11, 11, 19
+; POWERPC_64LE-NEXT: vcmpequh 18, 18, 3
+; POWERPC_64LE-NEXT: xxlnor 50, 50, 50
+; POWERPC_64LE-NEXT: vmrghh 19, 18, 18
+; POWERPC_64LE-NEXT: vmrglh 18, 18, 18
+; POWERPC_64LE-NEXT: xxland 51, 51, 34
+; POWERPC_64LE-NEXT: xxland 50, 50, 34
+; POWERPC_64LE-NEXT: vadduwm 17, 17, 19
+; POWERPC_64LE-NEXT: lxv 51, 48(4)
+; POWERPC_64LE-NEXT: addi 4, 4, 128
+; POWERPC_64LE-NEXT: vadduwm 13, 13, 18
+; POWERPC_64LE-NEXT: vcmpequh 19, 19, 3
+; POWERPC_64LE-NEXT: xxlnor 51, 51, 51
+; POWERPC_64LE-NEXT: vmrghh 18, 19, 19
+; POWERPC_64LE-NEXT: xxland 50, 50, 34
+; POWERPC_64LE-NEXT: vadduwm 16, 16, 18
+; POWERPC_64LE-NEXT: vmrglh 18, 19, 19
+; POWERPC_64LE-NEXT: xxland 50, 50, 34
+; POWERPC_64LE-NEXT: vadduwm 15, 15, 18
+; POWERPC_64LE-NEXT: bdnz .LBB0_6
+; POWERPC_64LE-NEXT: # %bb.7: # %middle.block
+; POWERPC_64LE-NEXT: vadduwm 3, 0, 4
+; POWERPC_64LE-NEXT: vadduwm 4, 7, 5
+; POWERPC_64LE-NEXT: li 4, 0
+; POWERPC_64LE-NEXT: cmpld 6, 5
+; POWERPC_64LE-NEXT: vadduwm 4, 10, 4
+; POWERPC_64LE-NEXT: vadduwm 3, 1, 3
+; POWERPC_64LE-NEXT: vadduwm 3, 8, 3
+; POWERPC_64LE-NEXT: vadduwm 4, 9, 4
+; POWERPC_64LE-NEXT: vadduwm 4, 14, 4
+; POWERPC_64LE-NEXT: vadduwm 3, 6, 3
+; POWERPC_64LE-NEXT: vadduwm 3, 11, 3
+; POWERPC_64LE-NEXT: vadduwm 4, 12, 4
+; POWERPC_64LE-NEXT: vadduwm 4, 17, 4
+; POWERPC_64LE-NEXT: vadduwm 3, 13, 3
+; POWERPC_64LE-NEXT: vadduwm 3, 15, 3
+; POWERPC_64LE-NEXT: vadduwm 4, 16, 4
+; POWERPC_64LE-NEXT: vadduwm 3, 3, 4
+; POWERPC_64LE-NEXT: xxswapd 36, 35
+; POWERPC_64LE-NEXT: vadduwm 3, 3, 4
+; POWERPC_64LE-NEXT: xxspltw 36, 35, 2
+; POWERPC_64LE-NEXT: vadduwm 3, 3, 4
+; POWERPC_64LE-NEXT: vextuwrx 4, 4, 3
+; POWERPC_64LE-NEXT: beq 0, .LBB0_14
+; POWERPC_64LE-NEXT: # %bb.8: # %vec.epilog.iter.check
+; POWERPC_64LE-NEXT: andi. 8, 5, 56
+; POWERPC_64LE-NEXT: beq 0, .LBB0_12
+; POWERPC_64LE-NEXT: .LBB0_9: # %vec.epilog.ph
+; POWERPC_64LE-NEXT: mr 8, 6
+; POWERPC_64LE-NEXT: rlwinm 6, 5, 0, 1, 28
+; POWERPC_64LE-NEXT: rldimi 4, 7, 32, 0
+; POWERPC_64LE-NEXT: xxlxor 36, 36, 36
+; POWERPC_64LE-NEXT: xxlxor 37, 37, 37
+; POWERPC_64LE-NEXT: rldimi 7, 7, 32, 0
+; POWERPC_64LE-NEXT: mtvsrdd 35, 7, 4
+; POWERPC_64LE-NEXT: sub 7, 6, 8
+; POWERPC_64LE-NEXT: sldi 4, 8, 1
+; POWERPC_64LE-NEXT: addi 7, 7, -8
+; POWERPC_64LE-NEXT: add 4, 3, 4
+; POWERPC_64LE-NEXT: rldicl 7, 7, 61, 3
+; POWERPC_64LE-NEXT: addi 7, 7, 1
+; POWERPC_64LE-NEXT: mtctr 7
+; POWERPC_64LE-NEXT: .p2align 4
+; POWERPC_64LE-NEXT: .LBB0_10: # %vec.epilog.vector.body
; POWERPC_64LE-NEXT: #
-; POWERPC_64LE-NEXT: lxv [[R8:[0-9]+]], 0(4)
+; POWERPC_64LE-NEXT: lxv 32, 0(4)
; POWERPC_64LE-NEXT: addi 4, 4, 16
-; POWERPC_64LE-NEXT: vcmpequh [[R9:[0-9]+]], [[R9]], [[R10:[0-9]+]]
-; POWERPC_64LE-NEXT: xxlnor [[R8]], [[R8]], [[R8]]
-; POWERPC_64LE-NEXT: vmrglh [[R11:[0-9]+]], [[R9]], [[R9]]
-; POWERPC_64LE-NEXT: vmrghh [[R9]], [[R9]], [[R9]]
-; POWERPC_64LE-NEXT: xxland [[R12:[0-9]+]], [[R12]], [[R6]]
-; POWERPC_64LE-NEXT: xxland [[R8]], [[R8]], [[R6]]
-; POWERPC_64LE-NEXT: vadduwm [[R7]], [[R7]], [[R9]]
-; POWERPC_64LE-NEXT: vadduwm [[R3]], [[R3]], [[R11]]
+; POWERPC_64LE-NEXT: vcmpequh 0, 0, 4
+; POWERPC_64LE-NEXT: xxlnor 32, 32, 32
+; POWERPC_64LE-NEXT: vmrglh 1, 0, 0
+; POWERPC_64LE-NEXT: vmrghh 0, 0, 0
+; POWERPC_64LE-NEXT: xxland 33, 33, 34
+; POWERPC_64LE-NEXT: xxland 32, 32, 34
+; POWERPC_64LE-NEXT: vadduwm 5, 5, 0
+; POWERPC_64LE-NEXT: vadduwm 3, 3, 1
; POWERPC_64LE-NEXT: bdnz .LBB0_10
-; POWERPC_64LE: blr
+; POWERPC_64LE-NEXT: # %bb.11: # %vec.epilog.middle.block
+; POWERPC_64LE-NEXT: vadduwm 2, 3, 5
+; POWERPC_64LE-NEXT: li 4, 0
+; POWERPC_64LE-NEXT: cmpld 6, 5
+; POWERPC_64LE-NEXT: xxswapd 35, 34
+; POWERPC_64LE-NEXT: vadduwm 2, 2, 3
+; POWERPC_64LE-NEXT: xxspltw 35, 34, 2
+; POWERPC_64LE-NEXT: vadduwm 2, 2, 3
+; POWERPC_64LE-NEXT: vextuwrx 4, 4, 2
+; POWERPC_64LE-NEXT: beq 0, .LBB0_14
+; POWERPC_64LE-NEXT: .LBB0_12: # %for.body.preheader
+; POWERPC_64LE-NEXT: sldi 7, 6, 1
+; POWERPC_64LE-NEXT: sub 5, 5, 6
+; POWERPC_64LE-NEXT: add 3, 7, 3
+; POWERPC_64LE-NEXT: mtctr 5
+; POWERPC_64LE-NEXT: addi 3, 3, -2
+; POWERPC_64LE-NEXT: .p2align 5
+; POWERPC_64LE-NEXT: .LBB0_13: # %for.body
+; POWERPC_64LE-NEXT: #
+; POWERPC_64LE-NEXT: lhzu 5, 2(3)
+; POWERPC_64LE-NEXT: cntlzw 5, 5
+; POWERPC_64LE-NEXT: srwi 5, 5, 5
+; POWERPC_64LE-NEXT: xori 5, 5, 1
+; POWERPC_64LE-NEXT: add 4, 4, 5
+; POWERPC_64LE-NEXT: bdnz .LBB0_13
+; POWERPC_64LE-NEXT: .LBB0_14: # %for.cond.cleanup
+; POWERPC_64LE-NEXT: mr 3, 4
+; POWERPC_64LE-NEXT: blr
;
; POWERPC_64-LABEL: test_Greater_than:
-; POWERPC_64: L..BB0_6: # %vector.body
+; POWERPC_64: # %bb.0: # %entry
+; POWERPC_64-NEXT: cmpwi 4, 1
+; POWERPC_64-NEXT: blt 0, L..BB0_3
+; POWERPC_64-NEXT: # %bb.1: # %iter.check
+; POWERPC_64-NEXT: clrldi 5, 4, 32
+; POWERPC_64-NEXT: cmplwi 4, 7
+; POWERPC_64-NEXT: bgt 0, L..BB0_4
+; POWERPC_64-NEXT: # %bb.2:
+; POWERPC_64-NEXT: li 4, 0
+; POWERPC_64-NEXT: li 6, 0
+; POWERPC_64-NEXT: b L..BB0_12
+; POWERPC_64-NEXT: L..BB0_3:
+; POWERPC_64-NEXT: li 4, 0
+; POWERPC_64-NEXT: mr 3, 4
+; POWERPC_64-NEXT: blr
+; POWERPC_64-NEXT: L..BB0_4: # %vector.main.loop.iter.check
+; POWERPC_64-NEXT: vspltisw 2, 1
+; POWERPC_64-NEXT: li 7, 0
+; POWERPC_64-NEXT: li 6, 0
+; POWERPC_64-NEXT: cmplwi 4, 64
+; POWERPC_64-NEXT: li 4, 0
+; POWERPC_64-NEXT: blt 0, L..BB0_9
+; POWERPC_64-NEXT: # %bb.5: # %vector.ph
+; POWERPC_64-NEXT: rlwinm 6, 5, 0, 1, 25
+; POWERPC_64-NEXT: addi 4, 3, 64
+; POWERPC_64-NEXT: xxlxor 35, 35, 35
+; POWERPC_64-NEXT: addi 8, 6, -64
+; POWERPC_64-NEXT: xxlxor 36, 36, 36
+; POWERPC_64-NEXT: rldicl 8, 8, 58, 6
+; POWERPC_64-NEXT: xxlxor 37, 37, 37
+; POWERPC_64-NEXT: xxlxor 32, 32, 32
+; POWERPC_64-NEXT: xxlxor 39, 39, 39
+; POWERPC_64-NEXT: xxlxor 33, 33, 33
+; POWERPC_64-NEXT: xxlxor 42, 42, 42
+; POWERPC_64-NEXT: xxlxor 40, 40, 40
+; POWERPC_64-NEXT: addi 8, 8, 1
+; POWERPC_64-NEXT: xxlxor 41, 41, 41
+; POWERPC_64-NEXT: mtctr 8
+; POWERPC_64-NEXT: xxlxor 38, 38, 38
+; POWERPC_64-NEXT: xxlxor 46, 46, 46
+; POWERPC_64-NEXT: xxlxor 43, 43, 43
+; POWERPC_64-NEXT: xxlxor 44, 44, 44
+; POWERPC_64-NEXT: xxlxor 45, 45, 45
+; POWERPC_64-NEXT: xxlxor 49, 49, 49
+; POWERPC_64-NEXT: xxlxor 47, 47, 47
+; POWERPC_64-NEXT: xxlxor 48, 48, 48
+; POWERPC_64-NEXT: .align 4
+; POWERPC_64-NEXT: L..BB0_6: # %vector.body
; POWERPC_64-NEXT: #
-; POWERPC_64-NEXT: lxv [[R1:[0-9]+]], -64(4)
-; POWERPC_64-NEXT: vcmpequh [[R2:[0-9]+]], [[R2]], [[R3:[0-9]+]]
-; POWERPC_64-NEXT: xxlnor [[R1]], [[R1]], [[R1]]
-; POWERPC_64-NEXT: vmrglh [[R4:[0-9]+]], [[R2]], [[R2]]
-; POWERPC_64-NEXT: vmrghh [[R2]], [[R2]], [[R2]]
-; POWERPC_64-NEXT: xxland [[R5:[0-9]+]], [[R5]], [[R6:[0-9]+]]
-; POWERPC_64-NEXT: xxland [[R1]], [[R1]], [[R6]]
-; POWERPC_64-NEXT: vadduwm [[R7:[0-9]+]], [[R7]], [[R4]]
-; POWERPC_64: L..BB0_10: # %vec.epilog.vector.body
+; POWERPC_64-NEXT: lxv 50, -64(4)
+; POWERPC_64-NEXT: vcmpequh 18, 18, 3
+; POWERPC_64-NEXT: xxlnor 50, 50, 50
+; POWERPC_64-NEXT: vmrglh 19, 18, 18
+; POWERPC_64-NEXT: vmrghh 18, 18, 18
+; POWERPC_64-NEXT: xxland 51, 51, 34
+; POWERPC_64-NEXT: xxland 50, 50, 34
+; POWERPC_64-NEXT: vadduwm 5, 5, 19
+; POWERPC_64-NEXT: lxv 51, -48(4)
+; POWERPC_64-NEXT: vadduwm 4, 4, 18
+; POWERPC_64-NEXT: vcmpequh 19, 19, 3
+; POWERPC_64-NEXT: xxlnor 51, 51, 51
+; POWERPC_64-NEXT: vmrglh 18, 19, 19
+; POWERPC_64-NEXT: vmrghh 19, 19, 19
+; POWERPC_64-NEXT: xxland 50, 50, 34
+; POWERPC_64-NEXT: xxland 51, 51, 34
+; POWERPC_64-NEXT: vadduwm 7, 7, 18
+; POWERPC_64-NEXT: lxv 50, -32(4)
+; POWERPC_64-NEXT: vadduwm 0, 0, 19
+; POWERPC_64-NEXT: vcmpequh 18, 18, 3
+; POWERPC_64-NEXT: xxlnor 50, 50, 50
+; POWERPC_64-NEXT: vmrglh 19, 18, 18
+; POWERPC_64-NEXT: vmrghh 18, 18, 18
+; POWERPC_64-NEXT: xxland 51, 51, 34
+; POWERPC_64-NEXT: xxland 50, 50, 34
+; POWERPC_64-NEXT: vadduwm 10, 10, 19
+; POWERPC_64-NEXT: lxv 51, -16(4)
+; POWERPC_64-NEXT: vadduwm 1, 1, 18
+; POWERPC_64-NEXT: vcmpequh 19, 19, 3
+; POWERPC_64-NEXT: xxlnor 51, 51, 51
+; POWERPC_64-NEXT: vmrglh 18, 19, 19
+; POWERPC_64-NEXT: vmrghh 19, 19, 19
+; POWERPC_64-NEXT: xxland 50, 50, 34
+; POWERPC_64-NEXT: xxland 51, 51, 34
+; POWERPC_64-NEXT: vadduwm 9, 9, 18
+; POWERPC_64-NEXT: lxv 50, 0(4)
+; POWERPC_64-NEXT: vadduwm 8, 8, 19
+; POWERPC_64-NEXT: vcmpequh 18, 18, 3
+; POWERPC_64-NEXT: xxlnor 50, 50, 50
+; POWERPC_64-NEXT: vmrglh 19, 18, 18
+; POWERPC_64-NEXT: vmrghh 18, 18, 18
+; POWERPC_64-NEXT: xxland 51, 51, 34
+; POWERPC_64-NEXT: xxland 50, 50, 34
+; POWERPC_64-NEXT: vadduwm 14, 14, 19
+; POWERPC_64-NEXT: lxv 51, 16(4)
+; POWERPC_64-NEXT: vadduwm 6, 6, 18
+; POWERPC_64-NEXT: vcmpequh 19, 19, 3
+; POWERPC_64-NEXT: xxlnor 51, 51, 51
+; POWERPC_64-NEXT: vmrglh 18, 19, 19
+; POWERPC_64-NEXT: vmrghh 19, 19, 19
+; POWERPC_64-NEXT: xxland 50, 50, 34
+; POWERPC_64-NEXT: xxland 51, 51, 34
+; POWERPC_64-NEXT: vadduwm 12, 12, 18
+; POWERPC_64-NEXT: lxv 50, 32(4)
+; POWERPC_64-NEXT: vadduwm 11, 11, 19
+; POWERPC_64-NEXT: vcmpequh 18, 18, 3
+; POWERPC_64-NEXT: xxlnor 50, 50, 50
+; POWERPC_64-NEXT: vmrglh 19, 18, 18
+; POWERPC_64-NEXT: vmrghh 18, 18, 18
+; POWERPC_64-NEXT: xxland 51, 51, 34
+; POWERPC_64-NEXT: xxland 50, 50, 34
+; POWERPC_64-NEXT: vadduwm 17, 17, 19
+; POWERPC_64-NEXT: lxv 51, 48(4)
+; POWERPC_64-NEXT: addi 4, 4, 128
+; POWERPC_64-NEXT: vadduwm 13, 13, 18
+; POWERPC_64-NEXT: vcmpequh 19, 19, 3
+; POWERPC_64-NEXT: xxlnor 51, 51, 51
+; POWERPC_64-NEXT: vmrglh 18, 19, 19
+; POWERPC_64-NEXT: xxland 50, 50, 34
+; POWERPC_64-NEXT: vadduwm 16, 16, 18
+; POWERPC_64-NEXT: vmrghh 18, 19, 19
+; POWERPC_64-NEXT: xxland 50, 50, 34
+; POWERPC_64-NEXT: vadduwm 15, 15, 18
+; POWERPC_64-NEXT: bdnz L..BB0_6
+; POWERPC_64-NEXT: # %bb.7: # %middle.block
+; POWERPC_64-NEXT: vadduwm 3, 0, 4
+; POWERPC_64-NEXT: vadduwm 4, 7, 5
+; POWERPC_64-NEXT: li 4, 0
+; POWERPC_64-NEXT: cmpld 6, 5
+; POWERPC_64-NEXT: vadduwm 4, 10, 4
+; POWERPC_64-NEXT: vadduwm 3, 1, 3
+; POWERPC_64-NEXT: vadduwm 3, 8, 3
+; POWERPC_64-NEXT: vadduwm 4, 9, 4
+; POWERPC_64-NEXT: vadduwm 4, 14, 4
+; POWERPC_64-NEXT: vadduwm 3, 6, 3
+; POWERPC_64-NEXT: vadduwm 3, 11, 3
+; POWERPC_64-NEXT: vadduwm 4, 12, 4
+; POWERPC_64-NEXT: vadduwm 4, 17, 4
+; POWERPC_64-NEXT: vadduwm 3, 13, 3
+; POWERPC_64-NEXT: vadduwm 3, 15, 3
+; POWERPC_64-NEXT: vadduwm 4, 16, 4
+; POWERPC_64-NEXT: vadduwm 3, 3, 4
+; POWERPC_64-NEXT: xxswapd 36, 35
+; POWERPC_64-NEXT: vadduwm 3, 3, 4
+; POWERPC_64-NEXT: xxspltw 36, 35, 1
+; POWERPC_64-NEXT: vadduwm 3, 3, 4
+; POWERPC_64-NEXT: vextuwlx 4, 4, 3
+; POWERPC_64-NEXT: beq 0, L..BB0_14
+; POWERPC_64-NEXT: # %bb.8: # %vec.epilog.iter.check
+; POWERPC_64-NEXT: andi. 8, 5, 56
+; POWERPC_64-NEXT: beq 0, L..BB0_12
+; POWERPC_64-NEXT: L..BB0_9: # %vec.epilog.ph
+; POWERPC_64-NEXT: li 9, 0
+; POWERPC_64-NEXT: mr 8, 6
+; POWERPC_64-NEXT: rlwinm 6, 5, 0, 1, 28
+; POWERPC_64-NEXT: rldimi 7, 7, 32, 0
+; POWERPC_64-NEXT: xxlxor 36, 36, 36
+; POWERPC_64-NEXT: rldimi 9, 4, 32, 0
+; POWERPC_64-NEXT: sldi 4, 8, 1
+; POWERPC_64-NEXT: xxlxor 37, 37, 37
+; POWERPC_64-NEXT: mtvsrdd 35, 9, 7
+; POWERPC_64-NEXT: sub 7, 6, 8
+; POWERPC_64-NEXT: add 4, 3, 4
+; POWERPC_64-NEXT: addi 7, 7, -8
+; POWERPC_64-NEXT: rldicl 7, 7, 61, 3
+; POWERPC_64-NEXT: addi 7, 7, 1
+; POWERPC_64-NEXT: mtctr 7
+; POWERPC_64-NEXT: .align 4
+; POWERPC_64-NEXT: L..BB0_10: # %vec.epilog.vector.body
; POWERPC_64-NEXT: #
-; POWERPC_64-NEXT: lxv [[R8:[0-9]+]], 0(4)
+; POWERPC_64-NEXT: lxv 32, 0(4)
; POWERPC_64-NEXT: addi 4, 4, 16
-; POWERPC_64-NEXT: vcmpequh [[R9:[0-9]+]], [[R9]], [[R10:[0-9]+]]
-; POWERPC_64-NEXT: xxlnor [[R8]], [[R8]], [[R8]]
-; POWERPC_64-NEXT: vmrghh [[R11:[0-9]+]], [[R9]], [[R9]]
-; POWERPC_64-NEXT: vmrglh [[R9]], [[R9]], [[R9]]
-; POWERPC_64-NEXT: xxland [[R12:[0-9]+]], [[R12]], [[R6]]
-; POWERPC_64-NEXT: xxland [[R8]], [[R8]], [[R6]]
-; POWERPC_64-NEXT: vadduwm [[R7]], [[R7]], [[R9]]
-; POWERPC_64-NEXT: vadduwm [[R3]], [[R3]], [[R11]]
+; POWERPC_64-NEXT: vcmpequh 0, 0, 4
+; POWERPC_64-NEXT: xxlnor 32, 32, 32
+; POWERPC_64-NEXT: vmrghh 1, 0, 0
+; POWERPC_64-NEXT: vmrglh 0, 0, 0
+; POWERPC_64-NEXT: xxland 33, 33, 34
+; POWERPC_64-NEXT: xxland 32, 32, 34
+; POWERPC_64-NEXT: vadduwm 5, 5, 0
+; POWERPC_64-NEXT: vadduwm 3, 3, 1
; POWERPC_64-NEXT: bdnz L..BB0_10
-; POWERPC_64: blr
+; POWERPC_64-NEXT: # %bb.11: # %vec.epilog.middle.block
+; POWERPC_64-NEXT: vadduwm 2, 3, 5
+; POWERPC_64-NEXT: li 4, 0
+; POWERPC_64-NEXT: cmpld 6, 5
+; POWERPC_64-NEXT: xxswapd 35, 34
+; POWERPC_64-NEXT: vadduwm 2, 2, 3
+; POWERPC_64-NEXT: xxspltw 35, 34, 1
+; POWERPC_64-NEXT: vadduwm 2, 2, 3
+; POWERPC_64-NEXT: vextuwlx 4, 4, 2
+; POWERPC_64-NEXT: beq 0, L..BB0_14
+; POWERPC_64-NEXT: L..BB0_12: # %for.body.preheader
+; POWERPC_64-NEXT: sldi 7, 6, 1
+; POWERPC_64-NEXT: sub 5, 5, 6
+; POWERPC_64-NEXT: add 3, 7, 3
+; POWERPC_64-NEXT: mtctr 5
+; POWERPC_64-NEXT: addi 3, 3, -2
+; POWERPC_64-NEXT: .align 5
+; POWERPC_64-NEXT: L..BB0_13: # %for.body
+; POWERPC_64-NEXT: #
+; POWERPC_64-NEXT: lhzu 5, 2(3)
+; POWERPC_64-NEXT: cntlzw 5, 5
+; POWERPC_64-NEXT: srwi 5, 5, 5
+; POWERPC_64-NEXT: xori 5, 5, 1
+; POWERPC_64-NEXT: add 4, 4, 5
+; POWERPC_64-NEXT: bdnz L..BB0_13
+; POWERPC_64-NEXT: L..BB0_14: # %for.cond.cleanup
+; POWERPC_64-NEXT: mr 3, 4
+; POWERPC_64-NEXT: blr
;
; POWERPC_32-LABEL: test_Greater_than:
-; POWERPC_32: L..BB0_7: # %vector.body
+; POWERPC_32: # %bb.0: # %entry
+; POWERPC_32-NEXT: cmpwi 4, 0
+; POWERPC_32-NEXT: ble 0, L..BB0_3
+; POWERPC_32-NEXT: # %bb.1: # %iter.check
+; POWERPC_32-NEXT: cmplwi 4, 7
+; POWERPC_32-NEXT: bgt 0, L..BB0_4
+; POWERPC_32-NEXT: # %bb.2:
+; POWERPC_32-NEXT: li 7, 0
+; POWERPC_32-NEXT: li 6, 0
+; POWERPC_32-NEXT: li 5, 0
+; POWERPC_32-NEXT: b L..BB0_13
+; POWERPC_32-NEXT: L..BB0_3:
+; POWERPC_32-NEXT: li 5, 0
+; POWERPC_32-NEXT: mr 3, 5
+; POWERPC_32-NEXT: blr
+; POWERPC_32-NEXT: L..BB0_4: # %vector.main.loop.iter.check
+; POWERPC_32-NEXT: lis 6, 32767
+; POWERPC_32-NEXT: vspltisw 2, 1
+; POWERPC_32-NEXT: li 5, 0
+; POWERPC_32-NEXT: cmplwi 4, 64
+; POWERPC_32-NEXT: ori 8, 6, 65472
+; POWERPC_32-NEXT: bge 0, L..BB0_6
+; POWERPC_32-NEXT: # %bb.5:
+; POWERPC_32-NEXT: li 7, 0
+; POWERPC_32-NEXT: li 6, 0
+; POWERPC_32-NEXT: b L..BB0_10
+; POWERPC_32-NEXT: L..BB0_6: # %vector.ph
+; POWERPC_32-NEXT: and 6, 4, 8
+; POWERPC_32-NEXT: xxlxor 35, 35, 35
+; POWERPC_32-NEXT: li 7, 0
+; POWERPC_32-NEXT: li 9, 0
+; POWERPC_32-NEXT: mr 10, 3
+; POWERPC_32-NEXT: xxlxor 36, 36, 36
+; POWERPC_32-NEXT: xxlxor 37, 37, 37
+; POWERPC_32-NEXT: xxlxor 39, 39, 39
+; POWERPC_32-NEXT: xxlxor 40, 40, 40
+; POWERPC_32-NEXT: xxlxor 32, 32, 32
+; POWERPC_32-NEXT: xxlxor 45, 45, 45
+; POWERPC_32-NEXT: xxlxor 41, 41, 41
+; POWERPC_32-NEXT: xxlxor 42, 42, 42
+; POWERPC_32-NEXT: xxlxor 33, 33, 33
+; POWERPC_32-NEXT: xxlxor 46, 46, 46
+; POWERPC_32-NEXT: xxlxor 43, 43, 43
+; POWERPC_32-NEXT: xxlxor 44, 44, 44
+; POWERPC_32-NEXT: xxlxor 38, 38, 38
+; POWERPC_32-NEXT: xxlxor 48, 48, 48
+; POWERPC_32-NEXT: xxlxor 47, 47, 47
+; POWERPC_32-NEXT: xxlxor 49, 49, 49
+; POWERPC_32-NEXT: .align 4
+; POWERPC_32-NEXT: L..BB0_7: # %vector.body
; POWERPC_32-NEXT: #
-; POWERPC_32-NEXT: lxv [[R1:[0-9]+]], 0(10)
-; POWERPC_32-NEXT: addic [[R13:[0-9]+]], [[R13]], 64
-; POWERPC_32-NEXT: addze [[R14:[0-9]+]], [[R14]]
-; POWERPC_32-NEXT: xor [[R15:[0-9]+]], [[R13]], [[R16:[0-9]+]]
-; POWERPC_32-NEXT: or. [[R15]], [[R15]], [[R14]]
-; POWERPC_32-NEXT: vcmpequh [[R2:[0-9]+]], [[R2]], [[R3:[0-9]+]]
-; POWERPC_32-NEXT: xxlnor [[R1]], [[R1]], [[R1]]
-; POWERPC_32-NEXT: vmrglh [[R4:[0-9]+]], [[R2]], [[R2]]
-; POWERPC_32-NEXT: vmrghh [[R2]], [[R2]], [[R2]]
-; POWERPC_32-NEXT: xxland [[R5:[0-9]+]], [[R5]], [[R6:[0-9]+]]
-; POWERPC_32-NEXT: xxland [[R1]], [[R1]], [[R6]]
-; POWERPC_32-NEXT: vadduwm [[R7:[0-9]+]], [[R7]], [[R4]]
-; POWERPC_32: L..BB0_11: # %vec.epilog.vector.body
+; POWERPC_32-NEXT: lxv 50, 0(10)
+; POWERPC_32-NEXT: addic 9, 9, 64
+; POWERPC_32-NEXT: addze 5, 5
+; POWERPC_32-NEXT: xor 11, 9, 6
+; POWERPC_32-NEXT: or. 11, 11, 5
+; POWERPC_32-NEXT: vcmpequh 18, 18, 3
+; POWERPC_32-NEXT: xxlnor 50, 50, 50
+; POWERPC_32-NEXT: vmrglh 19, 18, 18
+; POWERPC_32-NEXT: vmrghh 18, 18, 18
+; POWERPC_32-NEXT: xxland 51, 51, 34
+; POWERPC_32-NEXT: xxland 50, 50, 34
+; POWERPC_32-NEXT: vadduwm 5, 5, 19
+; POWERPC_32-NEXT: lxv 51, 16(10)
+; POWERPC_32-NEXT: vadduwm 4, 4, 18
+; POWERPC_32-NEXT: vcmpequh 19, 19, 3
+; POWERPC_32-NEXT: xxlnor 51, 51, 51
+; POWERPC_32-NEXT: vmrglh 18, 19, 19
+; POWERPC_32-NEXT: vmrghh 19, 19, 19
+; POWERPC_32-NEXT: xxland 50, 50, 34
+; POWERPC_32-NEXT: xxland 51, 51, 34
+; POWERPC_32-NEXT: vadduwm 8, 8, 18
+; POWERPC_32-NEXT: lxv 50, 32(10)
+; POWERPC_32-NEXT: vadduwm 7, 7, 19
+; POWERPC_32-NEXT: vcmpequh 18, 18, 3
+; POWERPC_32-NEXT: xxlnor 50, 50, 50
+; POWERPC_32-NEXT: vmrglh 19, 18, 18
+; POWERPC_32-NEXT: vmrghh 18, 18, 18
+; POWERPC_32-NEXT: xxland 51, 51, 34
+; POWERPC_32-NEXT: xxland 50, 50, 34
+; POWERPC_32-NEXT: vadduwm 13, 13, 19
+; POWERPC_32-NEXT: lxv 51, 48(10)
+; POWERPC_32-NEXT: vadduwm 0, 0, 18
+; POWERPC_32-NEXT: vcmpequh 19, 19, 3
+; POWERPC_32-NEXT: xxlnor 51, 51, 51
+; POWERPC_32-NEXT: vmrglh 18, 19, 19
+; POWERPC_32-NEXT: vmrghh 19, 19, 19
+; POWERPC_32-NEXT: xxland 50, 50, 34
+; POWERPC_32-NEXT: xxland 51, 51, 34
+; POWERPC_32-NEXT: vadduwm 10, 10, 18
+; POWERPC_32-NEXT: lxv 50, 64(10)
+; POWERPC_32-NEXT: vadduwm 9, 9, 19
+; POWERPC_32-NEXT: vcmpequh 18, 18, 3
+; POWERPC_32-NEXT: xxlnor 50, 50, 50
+; POWERPC_32-NEXT: vmrglh 19, 18, 18
+; POWERPC_32-NEXT: vmrghh 18, 18, 18
+; POWERPC_32-NEXT: xxland 51, 51, 34
+; POWERPC_32-NEXT: xxland 50, 50, 34
+; POWERPC_32-NEXT: vadduwm 14, 14, 19
+; POWERPC_32-NEXT: lxv 51, 80(10)
+; POWERPC_32-NEXT: vadduwm 1, 1, 18
+; POWERPC_32-NEXT: vcmpequh 19, 19, 3
+; POWERPC_32-NEXT: xxlnor 51, 51, 51
+; POWERPC_32-NEXT: vmrglh 18, 19, 19
+; POWERPC_32-NEXT: vmrghh 19, 19, 19
+; POWERPC_32-NEXT: xxland 50, 50, 34
+; POWERPC_32-NEXT: xxland 51, 51, 34
+; POWERPC_32-NEXT: vadduwm 12, 12, 18
+; POWERPC_32-NEXT: lxv 50, 96(10)
+; POWERPC_32-NEXT: vadduwm 11, 11, 19
+; POWERPC_32-NEXT: vcmpequh 18, 18, 3
+; POWERPC_32-NEXT: xxlnor 50, 50, 50
+; POWERPC_32-NEXT: vmrglh 19, 18, 18
+; POWERPC_32-NEXT: vmrghh 18, 18, 18
+; POWERPC_32-NEXT: xxland 51, 51, 34
+; POWERPC_32-NEXT: xxland 50, 50, 34
+; POWERPC_32-NEXT: vadduwm 16, 16, 19
+; POWERPC_32-NEXT: lxv 51, 112(10)
+; POWERPC_32-NEXT: vadduwm 6, 6, 18
+; POWERPC_32-NEXT: addi 10, 10, 128
+; POWERPC_32-NEXT: vcmpequh 19, 19, 3
+; POWERPC_32-NEXT: xxlnor 51, 51, 51
+; POWERPC_32-NEXT: vmrglh 18, 19, 19
+; POWERPC_32-NEXT: xxland 50, 50, 34
+; POWERPC_32-NEXT: vadduwm 17, 17, 18
+; POWERPC_32-NEXT: vmrghh 18, 19, 19
+; POWERPC_32-NEXT: xxland 50, 50, 34
+; POWERPC_32-NEXT: vadduwm 15, 15, 18
+; POWERPC_32-NEXT: bne 0, L..BB0_7
+; POWERPC_32-NEXT: # %bb.8: # %middle.block
+; POWERPC_32-NEXT: vadduwm 3, 7, 4
+; POWERPC_32-NEXT: vadduwm 4, 8, 5
+; POWERPC_32-NEXT: xor. 9, 6, 4
+; POWERPC_32-NEXT: vadduwm 4, 13, 4
+; POWERPC_32-NEXT: vadduwm 3, 0, 3
+; POWERPC_32-NEXT: vadduwm 3, 9, 3
+; POWERPC_32-NEXT: vadduwm 4, 10, 4
+; POWERPC_32-NEXT: vadduwm 4, 14, 4
+; POWERPC_32-NEXT: vadduwm 3, 1, 3
+; POWERPC_32-NEXT: vadduwm 3, 11, 3
+; POWERPC_32-NEXT: vadduwm 4, 12, 4
+; POWERPC_32-NEXT: vadduwm 4, 16, 4
+; POWERPC_32-NEXT: vadduwm 3, 6, 3
+; POWERPC_32-NEXT: vadduwm 3, 15, 3
+; POWERPC_32-NEXT: vadduwm 4, 17, 4
+; POWERPC_32-NEXT: vadduwm 3, 3, 4
+; POWERPC_32-NEXT: xxswapd 36, 35
+; POWERPC_32-NEXT: vadduwm 3, 3, 4
+; POWERPC_32-NEXT: xxspltw 36, 35, 1
+; POWERPC_32-NEXT: vadduwm 3, 3, 4
+; POWERPC_32-NEXT: stxv 35, -16(1)
+; POWERPC_32-NEXT: lwz 5, -16(1)
+; POWERPC_32-NEXT: beq 0, L..BB0_15
+; POWERPC_32-NEXT: # %bb.9: # %vec.epilog.iter.check
+; POWERPC_32-NEXT: andi. 9, 4, 56
+; POWERPC_32-NEXT: beq 0, L..BB0_13
+; POWERPC_32-NEXT: L..BB0_10: # %vec.epilog.ph
+; POWERPC_32-NEXT: stw 5, -32(1)
+; POWERPC_32-NEXT: lwz 5, L..C0(2) # %const.0
+; POWERPC_32-NEXT: xxlxor 36, 36, 36
+; POWERPC_32-NEXT: mr 9, 6
+; POWERPC_32-NEXT: lxv 1, -32(1)
+; POWERPC_32-NEXT: addi 6, 8, 56
+; POWERPC_32-NEXT: and 6, 4, 6
+; POWERPC_32-NEXT: xxlxor 35, 35, 35
+; POWERPC_32-NEXT: xxlxor 37, 37, 37
+; POWERPC_32-NEXT: lxv 0, 0(5)
+; POWERPC_32-NEXT: xxperm 36, 1, 0
+; POWERPC_32-NEXT: .align 4
+; POWERPC_32-NEXT: L..BB0_11: # %vec.epilog.vector.body
; POWERPC_32-NEXT: #
-; POWERPC_32-NEXT: slwi [[R14]], [[R13]], 1
-; POWERPC_32-NEXT: addic [[R13]], [[R13]], 8
-; POWERPC_32-NEXT: addze [[R17:[0-9]+]], [[R17]]
-; POWERPC_32-NEXT: lxvx [[R8:[0-9]+]], [[R18:[0-9]+]], [[R14]]
-; POWERPC_32-NEXT: xor [[R14]], [[R13]], [[R16]]
-; POWERPC_32-NEXT: or. [[R14]], [[R14]], [[R17]]
-; POWERPC_32-NEXT: vcmpequh [[R9:[0-9]+]], [[R9]], [[R3]]
-; POWERPC_32-NEXT: xxlnor [[R8]], [[R8]], [[R8]]
-; POWERPC_32-NEXT: vmrghh [[R11:[0-9]+]], [[R9]], [[R9]]
-; POWERPC_32-NEXT: vmrglh [[R9]], [[R9]], [[R9]]
-; POWERPC_32-NEXT: xxland [[R12:[0-9]+]], [[R12]], [[R6]]
-; POWERPC_32-NEXT: xxland [[R8]], [[R8]], [[R6]]
-; POWERPC_32-NEXT: vadduwm [[R7]], [[R7]], [[R9]]
-; POWERPC_32-NEXT: vadduwm [[R19:[0-9]+]], [[R19]], [[R11]]
+; POWERPC_32-NEXT: slwi 5, 9, 1
+; POWERPC_32-NEXT: addic 9, 9, 8
+; POWERPC_32-NEXT: addze 7, 7
+; POWERPC_32-NEXT: lxvx 32, 3, 5
+; POWERPC_32-NEXT: xor 5, 9, 6
+; POWERPC_32-NEXT: or. 5, 5, 7
+; POWERPC_32-NEXT: vcmpequh 0, 0, 3
+; POWERPC_32-NEXT: xxlnor 32, 32, 32
+; POWERPC_32-NEXT: vmrghh 1, 0, 0
+; POWERPC_32-NEXT: vmrglh 0, 0, 0
+; POWERPC_32-NEXT: xxland 33, 33, 34
+; POWERPC_32-NEXT: xxland 32, 32, 34
+; POWERPC_32-NEXT: vadduwm 5, 5, 0
+; POWERPC_32-NEXT: vadduwm 4, 4, 1
; POWERPC_32-NEXT: bne 0, L..BB0_11
-; POWERPC_32: blr
+; POWERPC_32-NEXT: # %bb.12: # %vec.epilog.middle.block
+; POWERPC_32-NEXT: vadduwm 2, 4, 5
+; POWERPC_32-NEXT: xor. 7, 6, 4
+; POWERPC_32-NEXT: li 7, 0
+; POWERPC_32-NEXT: xxswapd 35, 34
+; POWERPC_32-NEXT: vadduwm 2, 2, 3
+; POWERPC_32-NEXT: xxspltw 35, 34, 1
+; POWERPC_32-NEXT: vadduwm 2, 2, 3
+; POWERPC_32-NEXT: stxv 34, -48(1)
+; POWERPC_32-NEXT: lwz 5, -48(1)
+; POWERPC_32-NEXT: beq 0, L..BB0_15
+; POWERPC_32-NEXT: L..BB0_13: # %for.body.preheader
+; POWERPC_32-NEXT: slwi 8, 6, 1
+; POWERPC_32-NEXT: add 3, 8, 3
+; POWERPC_32-NEXT: addi 3, 3, -2
+; POWERPC_32-NEXT: .align 4
+; POWERPC_32-NEXT: L..BB0_14: # %for.body
+; POWERPC_32-NEXT: #
+; POWERPC_32-NEXT: lhzu 8, 2(3)
+; POWERPC_32-NEXT: addic 6, 6, 1
+; POWERPC_32-NEXT: addze 7, 7
+; POWERPC_32-NEXT: cntlzw 8, 8
+; POWERPC_32-NEXT: not 8, 8
+; POWERPC_32-NEXT: rlwinm 8, 8, 27, 31, 31
+; POWERPC_32-NEXT: add 5, 5, 8
+; POWERPC_32-NEXT: xor 8, 6, 4
+; POWERPC_32-NEXT: or. 8, 8, 7
+; POWERPC_32-NEXT: bne 0, L..BB0_14
+; POWERPC_32-NEXT: L..BB0_15: # %for.cond.cleanup
+; POWERPC_32-NEXT: mr 3, 5
+; POWERPC_32-NEXT: blr
entry:
%cmp5 = icmp sgt i32 %ncols, 0
br i1 %cmp5, label %iter.check, label %for.cond.cleanup
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