[llvm] [AArch64] Use CNEG for absolute difference patterns. (PR #151177)

[Ricardo Jesus via llvm-commits]

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@@ -11386,6 +11386,22 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(
       return DAG.getNode(ISD::AND, DL, VT, LHS, Shift);
     }
 
+    // Canonicalise absolute difference patterns:
+    //   select_cc lhs, rhs, sub(lhs, rhs), sub(rhs, lhs), cc ->
+    //   select_cc lhs, rhs, sub(lhs, rhs), neg(sub(lhs, rhs)), cc
+    //
+    //   select_cc lhs, rhs, sub(rhs, lhs), sub(lhs, rhs), cc ->
+    //   select_cc lhs, rhs, neg(sub(lhs, rhs)), sub(lhs, rhs), cc
+    // The second forms can be matched into subs+cneg.
+    if (TVal.getOpcode() == ISD::SUB && FVal.getOpcode() == ISD::SUB) {
+      if (TVal.getOperand(0) == LHS && TVal.getOperand(1) == RHS &&
+          FVal.getOperand(0) == RHS && FVal.getOperand(1) == LHS)
+        FVal = DAG.getNegative(TVal, DL, TVal.getValueType());
+      else if (TVal.getOperand(0) == RHS && TVal.getOperand(1) == LHS &&
+               FVal.getOperand(0) == LHS && FVal.getOperand(1) == RHS)
+        TVal = DAG.getNegative(FVal, DL, FVal.getValueType());
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rj-jesus wrote:

Hi @paulwalker-arm, apologies for this, but I believe I made a mistake here. I should have created new ISD::SUB nodes rather than reusing `TVal`/`FVal` for the negation, as doing the latter may be unsafe in the presence of flags ([alive2](https://alive2.llvm.org/ce/z/g9kRwM)). I haven't found practical cases of this causing issues, but what do you think, does this seem like something worth following up on?

https://github.com/llvm/llvm-project/pull/151177