[llvm] 342f212 - [AArch64] Regnerate and update a number of tests. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 3 23:42:03 PDT 2025
Author: David Green
Date: 2025-08-04T07:41:57+01:00
New Revision: 342f212d47ed90edcb8236125979941869fc6d42
URL: https://github.com/llvm/llvm-project/commit/342f212d47ed90edcb8236125979941869fc6d42
DIFF: https://github.com/llvm/llvm-project/commit/342f212d47ed90edcb8236125979941869fc6d42.diff
LOG: [AArch64] Regnerate and update a number of tests. NFC
extend_inreg_of_concat_subvectors.ll was using -mattr=+global-isel, which is
now replaced by -global-isel
Added:
Modified:
llvm/test/CodeGen/AArch64/arm64-ext.ll
llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
llvm/test/CodeGen/AArch64/arm64-vext.ll
llvm/test/CodeGen/AArch64/arm64-vext_reverse.ll
llvm/test/CodeGen/AArch64/extend_inreg_of_concat_subvectors.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/arm64-ext.ll b/llvm/test/CodeGen/AArch64/arm64-ext.ll
index 50df6a0388587..8bf2b826d7101 100644
--- a/llvm/test/CodeGen/AArch64/arm64-ext.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-ext.ll
@@ -135,3 +135,68 @@ define <2 x ptr> @test_v2p0(<2 x ptr> %a, <2 x ptr> %b) {
%s = shufflevector <2 x ptr> %a, <2 x ptr> %b, <2 x i32> <i32 3, i32 0>
ret <2 x ptr> %s
}
+
+define <16 x i8> @reverse_vector_s8x16b(<16 x i8> noundef %x) {
+; CHECK-SD-LABEL: reverse_vector_s8x16b:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: rev64 v1.16b, v0.16b
+; CHECK-SD-NEXT: ext v0.16b, v1.16b, v1.16b, #8
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: reverse_vector_s8x16b:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: rev64 v1.16b, v0.16b
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: ret
+entry:
+ %shuffle.i = shufflevector <16 x i8> %x, <16 x i8> poison, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
+ %shuffle.i6 = shufflevector <16 x i8> %shuffle.i, <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %shuffle.i7 = shufflevector <16 x i8> %shuffle.i, <16 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %shuffle.i5 = shufflevector <8 x i8> %shuffle.i6, <8 x i8> %shuffle.i7, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i8> %shuffle.i5
+}
+
+define <8 x i16> @reverse_vector_s16x8b(<8 x i16> noundef %x) {
+; CHECK-SD-LABEL: reverse_vector_s16x8b:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: rev64 v1.8h, v0.8h
+; CHECK-SD-NEXT: ext v0.16b, v1.16b, v1.16b, #8
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: reverse_vector_s16x8b:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: rev64 v1.8h, v0.8h
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: ret
+entry:
+ %shuffle.i = shufflevector <8 x i16> %x, <8 x i16> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
+ %shuffle.i6 = shufflevector <8 x i16> %shuffle.i, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %shuffle.i7 = shufflevector <8 x i16> %shuffle.i, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %shuffle.i5 = shufflevector <4 x i16> %shuffle.i6, <4 x i16> %shuffle.i7, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i16> %shuffle.i5
+}
+
+define <4 x i32> @reverse_vector_s32x4b(<4 x i32> noundef %x) {
+; CHECK-SD-LABEL: reverse_vector_s32x4b:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: rev64 v0.4s, v0.4s
+; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: reverse_vector_s32x4b:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: rev64 v1.4s, v0.4s
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: ret
+entry:
+ %shuffle.i = shufflevector <4 x i32> %x, <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+ %shuffle.i6 = shufflevector <4 x i32> %shuffle.i, <4 x i32> poison, <2 x i32> <i32 2, i32 3>
+ %shuffle.i7 = shufflevector <4 x i32> %shuffle.i, <4 x i32> poison, <2 x i32> <i32 0, i32 1>
+ %shuffle.i5 = shufflevector <2 x i32> %shuffle.i6, <2 x i32> %shuffle.i7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x i32> %shuffle.i5
+}
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
index 367105f783817..f4e59fe2eb249 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
@@ -1708,7 +1708,7 @@ define <16 x i8> @test_concat_v16i8_v8i8_v16i8(<8 x i8> %x, <16 x i8> %y) #0 {
; CHECK-GI-LABEL: test_concat_v16i8_v8i8_v16i8:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov v2.16b, v1.16b
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 def $q0 def $q0 def $q0 def $q0 def $q0 def $q0 def $q0
; CHECK-GI-NEXT: adrp x8, .LCPI127_0
; CHECK-GI-NEXT: mov v1.b[0], v0.b[0]
; CHECK-GI-NEXT: mov v1.b[1], v0.b[1]
@@ -1752,7 +1752,7 @@ define <16 x i8> @test_concat_v16i8_v16i8_v8i8(<16 x i8> %x, <8 x i8> %y) #0 {
; CHECK-GI-LABEL: test_concat_v16i8_v16i8_v8i8:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov b2, v0.b[0]
-; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 def $q1 def $q1 def $q1 def $q1 def $q1 def $q1 def $q1
; CHECK-GI-NEXT: mov v2.b[1], v0.b[1]
; CHECK-GI-NEXT: mov v2.b[2], v0.b[2]
; CHECK-GI-NEXT: mov v2.b[3], v0.b[3]
@@ -1816,9 +1816,9 @@ define <16 x i8> @test_concat_v16i8_v8i8_v8i8(<8 x i8> %x, <8 x i8> %y) #0 {
;
; CHECK-GI-LABEL: test_concat_v16i8_v8i8_v8i8:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 def $q0 def $q0 def $q0 def $q0 def $q0 def $q0 def $q0
; CHECK-GI-NEXT: mov v2.b[0], v0.b[0]
-; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 def $q1 def $q1 def $q1 def $q1 def $q1 def $q1 def $q1
; CHECK-GI-NEXT: mov v2.b[1], v0.b[1]
; CHECK-GI-NEXT: mov v2.b[2], v0.b[2]
; CHECK-GI-NEXT: mov v2.b[3], v0.b[3]
@@ -1901,7 +1901,7 @@ define <8 x i16> @test_concat_v8i16_v4i16_v8i16(<4 x i16> %x, <8 x i16> %y) #0 {
; CHECK-GI-LABEL: test_concat_v8i16_v4i16_v8i16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov v2.16b, v1.16b
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 def $q0 def $q0 def $q0
; CHECK-GI-NEXT: adrp x8, .LCPI131_0
; CHECK-GI-NEXT: mov v1.h[0], v0.h[0]
; CHECK-GI-NEXT: mov v1.h[1], v0.h[1]
@@ -1933,7 +1933,7 @@ define <8 x i16> @test_concat_v8i16_v8i16_v4i16(<8 x i16> %x, <4 x i16> %y) #0 {
; CHECK-GI-LABEL: test_concat_v8i16_v8i16_v4i16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov h2, v0.h[0]
-; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 def $q1 def $q1 def $q1
; CHECK-GI-NEXT: mov v2.h[1], v0.h[1]
; CHECK-GI-NEXT: mov v2.h[2], v0.h[2]
; CHECK-GI-NEXT: mov v2.h[3], v0.h[3]
@@ -1973,9 +1973,9 @@ define <8 x i16> @test_concat_v8i16_v4i16_v4i16(<4 x i16> %x, <4 x i16> %y) #0 {
;
; CHECK-GI-LABEL: test_concat_v8i16_v4i16_v4i16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 def $q0 def $q0 def $q0
; CHECK-GI-NEXT: mov v2.h[0], v0.h[0]
-; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 def $q1 def $q1 def $q1
; CHECK-GI-NEXT: mov v2.h[1], v0.h[1]
; CHECK-GI-NEXT: mov v2.h[2], v0.h[2]
; CHECK-GI-NEXT: mov v2.h[3], v0.h[3]
@@ -2034,7 +2034,7 @@ define <4 x i32> @test_concat_v4i32_v2i32_v4i32(<2 x i32> %x, <4 x i32> %y) #0 {
; CHECK-GI-LABEL: test_concat_v4i32_v2i32_v4i32:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov v2.16b, v1.16b
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 def $q0
; CHECK-GI-NEXT: adrp x8, .LCPI135_0
; CHECK-GI-NEXT: mov v1.s[0], v0.s[0]
; CHECK-GI-NEXT: mov v1.s[1], v0.s[1]
@@ -2060,7 +2060,7 @@ define <4 x i32> @test_concat_v4i32_v4i32_v2i32(<4 x i32> %x, <2 x i32> %y) #0 {
; CHECK-GI-LABEL: test_concat_v4i32_v4i32_v2i32:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov s2, v0.s[0]
-; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 def $q1
; CHECK-GI-NEXT: mov v2.s[1], v0.s[1]
; CHECK-GI-NEXT: mov v2.s[2], v1.s[0]
; CHECK-GI-NEXT: mov v2.s[3], v1.s[1]
diff --git a/llvm/test/CodeGen/AArch64/arm64-vext.ll b/llvm/test/CodeGen/AArch64/arm64-vext.ll
index a56bd6b4e2f21..e522c0538c0e6 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vext.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vext.ll
@@ -1,8 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define void @test_vext_s8() nounwind ssp {
- ; CHECK-LABEL: test_vext_s8:
- ; CHECK: {{ext.8.*#1}}
+; CHECK-LABEL: test_vext_s8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: ldr d0, [sp, #24]
+; CHECK-NEXT: ext.8b v1, v0, v0, #1
+; CHECK-NEXT: stp d0, d0, [sp, #8]
+; CHECK-NEXT: str d1, [sp, #24]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
%xS8x8 = alloca <8 x i8>, align 8
%__a = alloca <8 x i8>, align 8
%__b = alloca <8 x i8>, align 8
@@ -18,8 +26,15 @@ define void @test_vext_s8() nounwind ssp {
}
define void @test_vext_u8() nounwind ssp {
- ; CHECK-LABEL: test_vext_u8:
- ; CHECK: {{ext.8.*#2}}
+; CHECK-LABEL: test_vext_u8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: ldr d0, [sp, #24]
+; CHECK-NEXT: ext.8b v1, v0, v0, #2
+; CHECK-NEXT: stp d0, d0, [sp, #8]
+; CHECK-NEXT: str d1, [sp, #24]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
%xU8x8 = alloca <8 x i8>, align 8
%__a = alloca <8 x i8>, align 8
%__b = alloca <8 x i8>, align 8
@@ -35,8 +50,15 @@ define void @test_vext_u8() nounwind ssp {
}
define void @test_vext_p8() nounwind ssp {
- ; CHECK-LABEL: test_vext_p8:
- ; CHECK: {{ext.8.*#3}}
+; CHECK-LABEL: test_vext_p8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: ldr d0, [sp, #24]
+; CHECK-NEXT: ext.8b v1, v0, v0, #3
+; CHECK-NEXT: stp d0, d0, [sp, #8]
+; CHECK-NEXT: str d1, [sp, #24]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
%xP8x8 = alloca <8 x i8>, align 8
%__a = alloca <8 x i8>, align 8
%__b = alloca <8 x i8>, align 8
@@ -52,8 +74,15 @@ define void @test_vext_p8() nounwind ssp {
}
define void @test_vext_s16() nounwind ssp {
- ; CHECK-LABEL: test_vext_s16:
- ; CHECK: {{ext.8.*#2}}
+; CHECK-LABEL: test_vext_s16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: ldr d0, [sp, #24]
+; CHECK-NEXT: ext.8b v1, v0, v0, #2
+; CHECK-NEXT: stp d0, d0, [sp, #8]
+; CHECK-NEXT: str d1, [sp, #24]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
%xS16x4 = alloca <4 x i16>, align 8
%__a = alloca <4 x i16>, align 8
%__b = alloca <4 x i16>, align 8
@@ -73,8 +102,15 @@ define void @test_vext_s16() nounwind ssp {
}
define void @test_vext_u16() nounwind ssp {
- ; CHECK-LABEL: test_vext_u16:
- ; CHECK: {{ext.8.*#4}}
+; CHECK-LABEL: test_vext_u16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: ldr d0, [sp, #24]
+; CHECK-NEXT: ext.8b v1, v0, v0, #4
+; CHECK-NEXT: stp d0, d0, [sp, #8]
+; CHECK-NEXT: str d1, [sp, #24]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
%xU16x4 = alloca <4 x i16>, align 8
%__a = alloca <4 x i16>, align 8
%__b = alloca <4 x i16>, align 8
@@ -94,8 +130,15 @@ define void @test_vext_u16() nounwind ssp {
}
define void @test_vext_p16() nounwind ssp {
- ; CHECK-LABEL: test_vext_p16:
- ; CHECK: {{ext.8.*#6}}
+; CHECK-LABEL: test_vext_p16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: ldr d0, [sp, #24]
+; CHECK-NEXT: ext.8b v1, v0, v0, #6
+; CHECK-NEXT: stp d0, d0, [sp, #8]
+; CHECK-NEXT: str d1, [sp, #24]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
%xP16x4 = alloca <4 x i16>, align 8
%__a = alloca <4 x i16>, align 8
%__b = alloca <4 x i16>, align 8
@@ -115,8 +158,15 @@ define void @test_vext_p16() nounwind ssp {
}
define void @test_vext_s32() nounwind ssp {
- ; CHECK-LABEL: test_vext_s32:
- ; CHECK: {{rev64.2s.*}}
+; CHECK-LABEL: test_vext_s32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: ldr d0, [sp, #24]
+; CHECK-NEXT: rev64.2s v1, v0
+; CHECK-NEXT: stp d0, d0, [sp, #8]
+; CHECK-NEXT: str d1, [sp, #24]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
%xS32x2 = alloca <2 x i32>, align 8
%__a = alloca <2 x i32>, align 8
%__b = alloca <2 x i32>, align 8
@@ -136,8 +186,15 @@ define void @test_vext_s32() nounwind ssp {
}
define void @test_vext_u32() nounwind ssp {
- ; CHECK-LABEL: test_vext_u32:
- ; CHECK: {{rev64.2s.*}}
+; CHECK-LABEL: test_vext_u32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: ldr d0, [sp, #24]
+; CHECK-NEXT: rev64.2s v1, v0
+; CHECK-NEXT: stp d0, d0, [sp, #8]
+; CHECK-NEXT: str d1, [sp, #24]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
%xU32x2 = alloca <2 x i32>, align 8
%__a = alloca <2 x i32>, align 8
%__b = alloca <2 x i32>, align 8
@@ -157,8 +214,15 @@ define void @test_vext_u32() nounwind ssp {
}
define void @test_vext_f32() nounwind ssp {
- ; CHECK-LABEL: test_vext_f32:
- ; CHECK: {{rev64.2s.*}}
+; CHECK-LABEL: test_vext_f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: ldr d0, [sp, #24]
+; CHECK-NEXT: rev64.2s v1, v0
+; CHECK-NEXT: stp d0, d0, [sp, #8]
+; CHECK-NEXT: str d1, [sp, #24]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
%xF32x2 = alloca <2 x float>, align 8
%__a = alloca <2 x float>, align 8
%__b = alloca <2 x float>, align 8
@@ -178,7 +242,13 @@ define void @test_vext_f32() nounwind ssp {
}
define void @test_vext_s64() nounwind ssp {
- ; CHECK-LABEL: test_vext_s64:
+; CHECK-LABEL: test_vext_s64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: ldr d0, [sp, #24]
+; CHECK-NEXT: stp d0, d0, [sp, #8]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
; CHECK_FIXME: {{rev64.2s.*}}
; this just turns into a load of the second element
%xS64x1 = alloca <1 x i64>, align 8
@@ -200,7 +270,13 @@ define void @test_vext_s64() nounwind ssp {
}
define void @test_vext_u64() nounwind ssp {
- ; CHECK-LABEL: test_vext_u64:
+; CHECK-LABEL: test_vext_u64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: ldr d0, [sp, #24]
+; CHECK-NEXT: stp d0, d0, [sp, #8]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
; CHECK_FIXME: {{ext.8.*#1}}
; this is turned into a simple load of the 2nd element
%xU64x1 = alloca <1 x i64>, align 8
@@ -222,8 +298,15 @@ define void @test_vext_u64() nounwind ssp {
}
define void @test_vextq_s8() nounwind ssp {
- ; CHECK-LABEL: test_vextq_s8:
- ; CHECK: {{ext.16.*#4}}
+; CHECK-LABEL: test_vextq_s8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ext.16b v1, v0, v0, #4
+; CHECK-NEXT: stp q0, q0, [sp]
+; CHECK-NEXT: str q1, [sp, #32]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: ret
%xS8x16 = alloca <16 x i8>, align 16
%__a = alloca <16 x i8>, align 16
%__b = alloca <16 x i8>, align 16
@@ -239,8 +322,15 @@ define void @test_vextq_s8() nounwind ssp {
}
define void @test_vextq_u8() nounwind ssp {
- ; CHECK-LABEL: test_vextq_u8:
- ; CHECK: {{ext.16.*#5}}
+; CHECK-LABEL: test_vextq_u8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ext.16b v1, v0, v0, #5
+; CHECK-NEXT: stp q0, q0, [sp]
+; CHECK-NEXT: str q1, [sp, #32]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: ret
%xU8x16 = alloca <16 x i8>, align 16
%__a = alloca <16 x i8>, align 16
%__b = alloca <16 x i8>, align 16
@@ -256,8 +346,15 @@ define void @test_vextq_u8() nounwind ssp {
}
define void @test_vextq_p8() nounwind ssp {
- ; CHECK-LABEL: test_vextq_p8:
- ; CHECK: {{ext.16.*#6}}
+; CHECK-LABEL: test_vextq_p8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ext.16b v1, v0, v0, #6
+; CHECK-NEXT: stp q0, q0, [sp]
+; CHECK-NEXT: str q1, [sp, #32]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: ret
%xP8x16 = alloca <16 x i8>, align 16
%__a = alloca <16 x i8>, align 16
%__b = alloca <16 x i8>, align 16
@@ -273,8 +370,15 @@ define void @test_vextq_p8() nounwind ssp {
}
define void @test_vextq_s16() nounwind ssp {
- ; CHECK-LABEL: test_vextq_s16:
- ; CHECK: {{ext.16.*#14}}
+; CHECK-LABEL: test_vextq_s16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ext.16b v1, v0, v0, #14
+; CHECK-NEXT: stp q0, q0, [sp]
+; CHECK-NEXT: str q1, [sp, #32]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: ret
%xS16x8 = alloca <8 x i16>, align 16
%__a = alloca <8 x i16>, align 16
%__b = alloca <8 x i16>, align 16
@@ -294,8 +398,15 @@ define void @test_vextq_s16() nounwind ssp {
}
define void @test_vextq_u16() nounwind ssp {
- ; CHECK-LABEL: test_vextq_u16:
- ; CHECK: {{ext.16.*#8}}
+; CHECK-LABEL: test_vextq_u16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ext.16b v1, v0, v0, #8
+; CHECK-NEXT: stp q0, q0, [sp]
+; CHECK-NEXT: str q1, [sp, #32]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: ret
%xU16x8 = alloca <8 x i16>, align 16
%__a = alloca <8 x i16>, align 16
%__b = alloca <8 x i16>, align 16
@@ -315,8 +426,15 @@ define void @test_vextq_u16() nounwind ssp {
}
define void @test_vextq_p16() nounwind ssp {
- ; CHECK-LABEL: test_vextq_p16:
- ; CHECK: {{ext.16.*#10}}
+; CHECK-LABEL: test_vextq_p16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ext.16b v1, v0, v0, #10
+; CHECK-NEXT: stp q0, q0, [sp]
+; CHECK-NEXT: str q1, [sp, #32]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: ret
%xP16x8 = alloca <8 x i16>, align 16
%__a = alloca <8 x i16>, align 16
%__b = alloca <8 x i16>, align 16
@@ -336,8 +454,15 @@ define void @test_vextq_p16() nounwind ssp {
}
define void @test_vextq_s32() nounwind ssp {
- ; CHECK-LABEL: test_vextq_s32:
- ; CHECK: {{ext.16.*#4}}
+; CHECK-LABEL: test_vextq_s32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ext.16b v1, v0, v0, #4
+; CHECK-NEXT: stp q0, q0, [sp]
+; CHECK-NEXT: str q1, [sp, #32]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: ret
%xS32x4 = alloca <4 x i32>, align 16
%__a = alloca <4 x i32>, align 16
%__b = alloca <4 x i32>, align 16
@@ -357,8 +482,15 @@ define void @test_vextq_s32() nounwind ssp {
}
define void @test_vextq_u32() nounwind ssp {
- ; CHECK-LABEL: test_vextq_u32:
- ; CHECK: {{ext.16.*#8}}
+; CHECK-LABEL: test_vextq_u32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ext.16b v1, v0, v0, #8
+; CHECK-NEXT: stp q0, q0, [sp]
+; CHECK-NEXT: str q1, [sp, #32]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: ret
%xU32x4 = alloca <4 x i32>, align 16
%__a = alloca <4 x i32>, align 16
%__b = alloca <4 x i32>, align 16
@@ -378,8 +510,15 @@ define void @test_vextq_u32() nounwind ssp {
}
define void @test_vextq_f32() nounwind ssp {
- ; CHECK-LABEL: test_vextq_f32:
- ; CHECK: {{ext.16.*#12}}
+; CHECK-LABEL: test_vextq_f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ext.16b v1, v0, v0, #12
+; CHECK-NEXT: stp q0, q0, [sp]
+; CHECK-NEXT: str q1, [sp, #32]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: ret
%xF32x4 = alloca <4 x float>, align 16
%__a = alloca <4 x float>, align 16
%__b = alloca <4 x float>, align 16
@@ -399,8 +538,15 @@ define void @test_vextq_f32() nounwind ssp {
}
define void @test_vextq_s64() nounwind ssp {
- ; CHECK-LABEL: test_vextq_s64:
- ; CHECK: {{ext.16.*#8}}
+; CHECK-LABEL: test_vextq_s64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ext.16b v1, v0, v0, #8
+; CHECK-NEXT: stp q0, q0, [sp]
+; CHECK-NEXT: str q1, [sp, #32]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: ret
%xS64x2 = alloca <2 x i64>, align 16
%__a = alloca <2 x i64>, align 16
%__b = alloca <2 x i64>, align 16
@@ -420,8 +566,15 @@ define void @test_vextq_s64() nounwind ssp {
}
define void @test_vextq_u64() nounwind ssp {
- ; CHECK-LABEL: test_vextq_u64:
- ; CHECK: {{ext.16.*#8}}
+; CHECK-LABEL: test_vextq_u64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ext.16b v1, v0, v0, #8
+; CHECK-NEXT: stp q0, q0, [sp]
+; CHECK-NEXT: str q1, [sp, #32]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: ret
%xU64x2 = alloca <2 x i64>, align 16
%__a = alloca <2 x i64>, align 16
%__b = alloca <2 x i64>, align 16
@@ -445,18 +598,21 @@ define void @test_vextq_u64() nounwind ssp {
; rdar://12051674
define <16 x i8> @vext1(<16 x i8> %_a) nounwind {
; CHECK-LABEL: vext1:
-; CHECK: ext.16b v0, v0, v0, #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext.16b v0, v0, v0, #8
+; CHECK-NEXT: ret
%vext = shufflevector <16 x i8> %_a, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <16 x i8> %vext
}
; <rdar://problem/12212062>
define <2 x i64> @vext2(<2 x i64> %p0, <2 x i64> %p1) nounwind readnone ssp {
-entry:
; CHECK-LABEL: vext2:
-; CHECK: add.2d v0, v0, v1
-; CHECK-NEXT: ext.16b v0, v0, v0, #8
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: add.2d v0, v0, v1
+; CHECK-NEXT: ext.16b v0, v0, v0, #8
+; CHECK-NEXT: ret
+entry:
%t0 = shufflevector <2 x i64> %p1, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
%t1 = shufflevector <2 x i64> %p0, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
%t2 = add <2 x i64> %t1, %t0
diff --git a/llvm/test/CodeGen/AArch64/arm64-vext_reverse.ll b/llvm/test/CodeGen/AArch64/arm64-vext_reverse.ll
index c51ea172232a7..9829ca392e11f 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vext_reverse.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vext_reverse.ll
@@ -1,172 +1,217 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=arm64-linux-gnuabi < %s | FileCheck %s
-; The following tests is to check the correctness of reversing input operand
+; The following tests is to check the correctness of reversing input operand
; of vext by enumerating all cases of using two undefs in shuffle masks.
define <4 x i16> @vext_6701_0(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_6701_0:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #4
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #4
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_12(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_6701_12:
-; CHECK: dup v0.2s, v0.s[0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.2s, v0.s[0]
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_13(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_6701_13:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #4
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #4
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 7, i32 undef, i32 1>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_14(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_6701_14:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #4
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #4
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 7, i32 0, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_23(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_6701_23:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #4
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #4
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 undef, i32 undef, i32 1>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_24(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_6701_24:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #4
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #4
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 undef, i32 0, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_34(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_6701_34:
-; CHECK: dup v0.2s, v1.s[1]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: dup v0.2s, v1.s[1]
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 7, i32 undef, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_0(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_5670_0:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 6, i32 7, i32 0>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_12(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_5670_12:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 7, i32 0>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_13(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_5670_13:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 6, i32 undef, i32 0>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_14(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_5670_14:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 6, i32 7, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_23(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_5670_23:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 undef, i32 undef, i32 0>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_24(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_5670_24:
-; CHECK: rev32 v0.4h, v1.4h
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev32 v0.4h, v1.4h
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 undef, i32 7, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_34(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_5670_34:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 6, i32 undef, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_0(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_7012_0:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #6
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #6
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 0, i32 1, i32 2>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_12(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_7012_12:
-; CHECK: ext v0.8b, v0.8b, v0.8b, #6
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v0.8b, v0.8b, #6
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 1, i32 2>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_13(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_7012_13:
-; CHECK: rev32 v0.4h, v0.4h
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev32 v0.4h, v0.4h
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 0, i32 undef, i32 2>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_14(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_7012_14:
-; CHECK: ext v0.8b, v0.8b, v0.8b, #6
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v0.8b, v0.8b, #6
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 0, i32 1, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_23(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_7012_23:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #6
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #6
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 undef, i32 undef, i32 2>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_24(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_7012_24:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #6
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #6
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 undef, i32 1, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_34(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_7012_34:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #6
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #6
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 0, i32 undef, i32 undef>
ret <4 x i16> %x
}
diff --git a/llvm/test/CodeGen/AArch64/extend_inreg_of_concat_subvectors.ll b/llvm/test/CodeGen/AArch64/extend_inreg_of_concat_subvectors.ll
index 1f1bfe6906482..6df8d2be6deab 100644
--- a/llvm/test/CodeGen/AArch64/extend_inreg_of_concat_subvectors.ll
+++ b/llvm/test/CodeGen/AArch64/extend_inreg_of_concat_subvectors.ll
@@ -1,20 +1,19 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=arm64-apple-ios -mattr=+sve -o - %s | FileCheck %s
-; RUN: llc -mtriple=aarch64_be-unknown-linux -mattr=+sve -o - %s | FileCheck --check-prefix=CHECK-BE %s
-; RUN: llc -mtriple=arm64-apple-ios -mattr=+global-isel -mattr=+sve -o - %s | FileCheck %s
-; RUN: llc -mtriple=aarch64_be-unknown-linux -mattr=+global-isel -mattr=+sve -o - %s | FileCheck --check-prefix=CHECK-BE %s
+; RUN: llc -mtriple=arm64-apple-ios -mattr=+sve -o - %s | FileCheck %s --check-prefix=CHECK-LE-SD
+; RUN: llc -mtriple=aarch64_be-unknown-linux -mattr=+sve -o - %s | FileCheck %s --check-prefix=CHECK-BE
+; RUN: llc -mtriple=arm64-apple-ios -global-isel -mattr=+sve -o - %s | FileCheck %s --check-prefix=CHECK-LE-GI
define void @zext_of_concat(ptr %a, ptr %b, ptr %c, ptr %d) nounwind {
-; CHECK-LABEL: zext_of_concat:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: add.2s v0, v0, v1
-; CHECK-NEXT: ldr q1, [x2]
-; CHECK-NEXT: ushll.2d v0, v0, #0
-; CHECK-NEXT: add.4s v0, v0, v1
-; CHECK-NEXT: str q0, [x2]
-; CHECK-NEXT: ret
+; CHECK-LE-SD-LABEL: zext_of_concat:
+; CHECK-LE-SD: ; %bb.0:
+; CHECK-LE-SD-NEXT: ldr d0, [x0]
+; CHECK-LE-SD-NEXT: ldr d1, [x1]
+; CHECK-LE-SD-NEXT: add.2s v0, v0, v1
+; CHECK-LE-SD-NEXT: ldr q1, [x2]
+; CHECK-LE-SD-NEXT: ushll.2d v0, v0, #0
+; CHECK-LE-SD-NEXT: add.4s v0, v0, v1
+; CHECK-LE-SD-NEXT: str q0, [x2]
+; CHECK-LE-SD-NEXT: ret
;
; CHECK-BE-LABEL: zext_of_concat:
; CHECK-BE: // %bb.0:
@@ -28,6 +27,23 @@ define void @zext_of_concat(ptr %a, ptr %b, ptr %c, ptr %d) nounwind {
; CHECK-BE-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-BE-NEXT: st1 { v0.4s }, [x2]
; CHECK-BE-NEXT: ret
+;
+; CHECK-LE-GI-LABEL: zext_of_concat:
+; CHECK-LE-GI: ; %bb.0:
+; CHECK-LE-GI-NEXT: ldr d0, [x0]
+; CHECK-LE-GI-NEXT: ldr d1, [x1]
+; CHECK-LE-GI-NEXT: movi.2d v3, #0000000000000000
+; CHECK-LE-GI-NEXT: Lloh0:
+; CHECK-LE-GI-NEXT: adrp x8, lCPI0_0 at PAGE
+; CHECK-LE-GI-NEXT: add.2s v2, v0, v1
+; CHECK-LE-GI-NEXT: Lloh1:
+; CHECK-LE-GI-NEXT: ldr q0, [x8, lCPI0_0 at PAGEOFF]
+; CHECK-LE-GI-NEXT: ldr q1, [x2]
+; CHECK-LE-GI-NEXT: tbl.16b v0, { v2, v3 }, v0
+; CHECK-LE-GI-NEXT: add.4s v0, v0, v1
+; CHECK-LE-GI-NEXT: str q0, [x2]
+; CHECK-LE-GI-NEXT: ret
+; CHECK-LE-GI-NEXT: .loh AdrpLdr Lloh0, Lloh1
%i0.a = load <2 x i32>, ptr %a
%i0.b = load <2 x i32>, ptr %b
%i0 = add <2 x i32> %i0.a, %i0.b
@@ -40,19 +56,19 @@ define void @zext_of_concat(ptr %a, ptr %b, ptr %c, ptr %d) nounwind {
}
define void @zext_of_concat_extrause(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e) nounwind {
-; CHECK-LABEL: zext_of_concat_extrause:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: ldr d0, [x1]
-; CHECK-NEXT: ldr d1, [x0]
-; CHECK-NEXT: add.2s v0, v1, v0
-; CHECK-NEXT: movi.2d v1, #0000000000000000
-; CHECK-NEXT: mov.d v0[1], v0[0]
-; CHECK-NEXT: zip1.4s v1, v0, v1
-; CHECK-NEXT: str q0, [x4]
-; CHECK-NEXT: ldr q0, [x2]
-; CHECK-NEXT: add.4s v0, v1, v0
-; CHECK-NEXT: str q0, [x2]
-; CHECK-NEXT: ret
+; CHECK-LE-SD-LABEL: zext_of_concat_extrause:
+; CHECK-LE-SD: ; %bb.0:
+; CHECK-LE-SD-NEXT: ldr d0, [x1]
+; CHECK-LE-SD-NEXT: ldr d1, [x0]
+; CHECK-LE-SD-NEXT: add.2s v0, v1, v0
+; CHECK-LE-SD-NEXT: movi.2d v1, #0000000000000000
+; CHECK-LE-SD-NEXT: mov.d v0[1], v0[0]
+; CHECK-LE-SD-NEXT: zip1.4s v1, v0, v1
+; CHECK-LE-SD-NEXT: str q0, [x4]
+; CHECK-LE-SD-NEXT: ldr q0, [x2]
+; CHECK-LE-SD-NEXT: add.4s v0, v1, v0
+; CHECK-LE-SD-NEXT: str q0, [x2]
+; CHECK-LE-SD-NEXT: ret
;
; CHECK-BE-LABEL: zext_of_concat_extrause:
; CHECK-BE: // %bb.0:
@@ -68,6 +84,25 @@ define void @zext_of_concat_extrause(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e) nou
; CHECK-BE-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-BE-NEXT: st1 { v0.4s }, [x2]
; CHECK-BE-NEXT: ret
+;
+; CHECK-LE-GI-LABEL: zext_of_concat_extrause:
+; CHECK-LE-GI: ; %bb.0:
+; CHECK-LE-GI-NEXT: ldr d0, [x0]
+; CHECK-LE-GI-NEXT: ldr d1, [x1]
+; CHECK-LE-GI-NEXT: movi.2d v3, #0000000000000000
+; CHECK-LE-GI-NEXT: Lloh2:
+; CHECK-LE-GI-NEXT: adrp x8, lCPI1_0 at PAGE
+; CHECK-LE-GI-NEXT: add.2s v2, v0, v1
+; CHECK-LE-GI-NEXT: Lloh3:
+; CHECK-LE-GI-NEXT: ldr q0, [x8, lCPI1_0 at PAGEOFF]
+; CHECK-LE-GI-NEXT: mov.d v2[1], v2[0]
+; CHECK-LE-GI-NEXT: tbl.16b v0, { v2, v3 }, v0
+; CHECK-LE-GI-NEXT: str q2, [x4]
+; CHECK-LE-GI-NEXT: ldr q1, [x2]
+; CHECK-LE-GI-NEXT: add.4s v0, v0, v1
+; CHECK-LE-GI-NEXT: str q0, [x2]
+; CHECK-LE-GI-NEXT: ret
+; CHECK-LE-GI-NEXT: .loh AdrpLdr Lloh2, Lloh3
%i0.a = load <2 x i32>, ptr %a
%i0.b = load <2 x i32>, ptr %b
%i0 = add <2 x i32> %i0.a, %i0.b
@@ -81,16 +116,16 @@ define void @zext_of_concat_extrause(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e) nou
}
define void @aext_of_concat(ptr %a, ptr %b, ptr %c, ptr %d) nounwind {
-; CHECK-LABEL: aext_of_concat:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: add.2s v0, v0, v1
-; CHECK-NEXT: ldr q1, [x2]
-; CHECK-NEXT: ushll.2d v0, v0, #0
-; CHECK-NEXT: add.4s v0, v0, v1
-; CHECK-NEXT: str q0, [x2]
-; CHECK-NEXT: ret
+; CHECK-LE-SD-LABEL: aext_of_concat:
+; CHECK-LE-SD: ; %bb.0:
+; CHECK-LE-SD-NEXT: ldr d0, [x0]
+; CHECK-LE-SD-NEXT: ldr d1, [x1]
+; CHECK-LE-SD-NEXT: add.2s v0, v0, v1
+; CHECK-LE-SD-NEXT: ldr q1, [x2]
+; CHECK-LE-SD-NEXT: ushll.2d v0, v0, #0
+; CHECK-LE-SD-NEXT: add.4s v0, v0, v1
+; CHECK-LE-SD-NEXT: str q0, [x2]
+; CHECK-LE-SD-NEXT: ret
;
; CHECK-BE-LABEL: aext_of_concat:
; CHECK-BE: // %bb.0:
@@ -102,6 +137,17 @@ define void @aext_of_concat(ptr %a, ptr %b, ptr %c, ptr %d) nounwind {
; CHECK-BE-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-BE-NEXT: st1 { v0.4s }, [x2]
; CHECK-BE-NEXT: ret
+;
+; CHECK-LE-GI-LABEL: aext_of_concat:
+; CHECK-LE-GI: ; %bb.0:
+; CHECK-LE-GI-NEXT: ldr d0, [x0]
+; CHECK-LE-GI-NEXT: ldr d1, [x1]
+; CHECK-LE-GI-NEXT: add.2s v0, v0, v1
+; CHECK-LE-GI-NEXT: ldr q1, [x2]
+; CHECK-LE-GI-NEXT: zip1.4s v0, v0, v0
+; CHECK-LE-GI-NEXT: add.4s v0, v0, v1
+; CHECK-LE-GI-NEXT: str q0, [x2]
+; CHECK-LE-GI-NEXT: ret
%i0.a = load <2 x i32>, ptr %a
%i0.b = load <2 x i32>, ptr %b
%i0 = add <2 x i32> %i0.a, %i0.b
@@ -114,19 +160,19 @@ define void @aext_of_concat(ptr %a, ptr %b, ptr %c, ptr %d) nounwind {
}
define void @aext_of_concat_extrause(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e) nounwind {
-; CHECK-LABEL: aext_of_concat_extrause:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: ldr d0, [x1]
-; CHECK-NEXT: ldr d1, [x0]
-; CHECK-NEXT: add.2s v0, v1, v0
-; CHECK-NEXT: mov.16b v1, v0
-; CHECK-NEXT: mov.d v1[1], v0[0]
-; CHECK-NEXT: zip1.4s v0, v0, v0
-; CHECK-NEXT: str q1, [x4]
-; CHECK-NEXT: ldr q1, [x2]
-; CHECK-NEXT: add.4s v0, v0, v1
-; CHECK-NEXT: str q0, [x2]
-; CHECK-NEXT: ret
+; CHECK-LE-SD-LABEL: aext_of_concat_extrause:
+; CHECK-LE-SD: ; %bb.0:
+; CHECK-LE-SD-NEXT: ldr d0, [x1]
+; CHECK-LE-SD-NEXT: ldr d1, [x0]
+; CHECK-LE-SD-NEXT: add.2s v0, v1, v0
+; CHECK-LE-SD-NEXT: mov.16b v1, v0
+; CHECK-LE-SD-NEXT: mov.d v1[1], v0[0]
+; CHECK-LE-SD-NEXT: zip1.4s v0, v0, v0
+; CHECK-LE-SD-NEXT: str q1, [x4]
+; CHECK-LE-SD-NEXT: ldr q1, [x2]
+; CHECK-LE-SD-NEXT: add.4s v0, v0, v1
+; CHECK-LE-SD-NEXT: str q0, [x2]
+; CHECK-LE-SD-NEXT: ret
;
; CHECK-BE-LABEL: aext_of_concat_extrause:
; CHECK-BE: // %bb.0:
@@ -141,6 +187,19 @@ define void @aext_of_concat_extrause(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e) nou
; CHECK-BE-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-BE-NEXT: st1 { v0.4s }, [x2]
; CHECK-BE-NEXT: ret
+;
+; CHECK-LE-GI-LABEL: aext_of_concat_extrause:
+; CHECK-LE-GI: ; %bb.0:
+; CHECK-LE-GI-NEXT: ldr d0, [x0]
+; CHECK-LE-GI-NEXT: ldr d1, [x1]
+; CHECK-LE-GI-NEXT: add.2s v0, v0, v1
+; CHECK-LE-GI-NEXT: mov.d v0[1], v0[0]
+; CHECK-LE-GI-NEXT: zip1.4s v1, v0, v0
+; CHECK-LE-GI-NEXT: str q0, [x4]
+; CHECK-LE-GI-NEXT: ldr q0, [x2]
+; CHECK-LE-GI-NEXT: add.4s v0, v1, v0
+; CHECK-LE-GI-NEXT: str q0, [x2]
+; CHECK-LE-GI-NEXT: ret
%i0.a = load <2 x i32>, ptr %a
%i0.b = load <2 x i32>, ptr %b
%i0 = add <2 x i32> %i0.a, %i0.b
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