[llvm] [LV] Peek through bitcasts when performing CSE (PR #146856)
Pedro Lobo via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 3 01:53:25 PDT 2025
https://github.com/pedroclobo updated https://github.com/llvm/llvm-project/pull/146856
>From 3b646c6ca2a294d50144863ee517c09e9ccef417 Mon Sep 17 00:00:00 2001
From: Pedro Lobo <pedro.lobo at tecnico.ulisboa.pt>
Date: Fri, 16 May 2025 13:02:12 +0100
Subject: [PATCH 1/4] [LoopVectorize] Peek through bitcasts when performing CSE
LoopVectorize performs CSE of induction variable instructions. Add
bitcasts to the worklist as well.
---
.../Transforms/Vectorize/LoopVectorize.cpp | 3 +-
.../Transforms/LoopVectorize/bitcast-cse.ll | 71 +++++++++++++++++++
2 files changed, 73 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/Transforms/LoopVectorize/bitcast-cse.ll
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 67df7a8af098d..81f859b903435 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -2643,7 +2643,8 @@ namespace {
struct CSEDenseMapInfo {
static bool canHandle(const Instruction *I) {
return isa<InsertElementInst>(I) || isa<ExtractElementInst>(I) ||
- isa<ShuffleVectorInst>(I) || isa<GetElementPtrInst>(I);
+ isa<ShuffleVectorInst>(I) || isa<GetElementPtrInst>(I) ||
+ isa<BitCastInst>(I);
}
static inline Instruction *getEmptyKey() {
diff --git a/llvm/test/Transforms/LoopVectorize/bitcast-cse.ll b/llvm/test/Transforms/LoopVectorize/bitcast-cse.ll
new file mode 100644
index 0000000000000..698a0d071acfe
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/bitcast-cse.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt %s -passes=loop-vectorize -S | FileCheck %s
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define i32 @bitcast-cse(i16 %0) {
+; CHECK-LABEL: define i32 @bitcast-cse(
+; CHECK-SAME: i16 [[TMP0:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i16> poison, i16 [[TMP0]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i16> [[BROADCAST_SPLATINSERT]], <4 x i16> poison, <4 x i32> zeroinitializer
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 4
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 16
+; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr null, i64 [[OFFSET_IDX]]
+; CHECK-NEXT: [[NEXT_GEP1:%.*]] = getelementptr i8, ptr null, i64 [[TMP1]]
+; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[BROADCAST_SPLAT]] to <4 x half>
+; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x half> [[TMP2]], <4 x half> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <8 x half> [[TMP3]], <8 x half> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
+; CHECK-NEXT: store <8 x half> [[INTERLEAVED_VEC]], ptr [[NEXT_GEP]], align 1
+; CHECK-NEXT: store <8 x half> [[INTERLEAVED_VEC]], ptr [[NEXT_GEP1]], align 1
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
+; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], -9223372036854775808
+; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br i1 true, label %[[FOR_END_LOOPEXIT909:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ null, %[[MIDDLE_BLOCK]] ], [ null, %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL3:%.*]] = phi i64 [ 0, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: br label %[[DO_BODY93_I705:.*]]
+; CHECK: [[DO_BODY93_I705]]:
+; CHECK-NEXT: [[DEST_10_I706:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[ADD_PTR97_I709:%.*]], %[[DO_BODY93_I705]] ]
+; CHECK-NEXT: [[LEN_ADDR_8_I707:%.*]] = phi i64 [ [[BC_RESUME_VAL3]], %[[SCALAR_PH]] ], [ [[SUB99_I710:%.*]], %[[DO_BODY93_I705]] ]
+; CHECK-NEXT: store i16 [[TMP0]], ptr [[DEST_10_I706]], align 1
+; CHECK-NEXT: [[ARRAYIDX96_I708:%.*]] = getelementptr i16, ptr [[DEST_10_I706]], i64 1
+; CHECK-NEXT: store half 0xH0000, ptr [[ARRAYIDX96_I708]], align 1
+; CHECK-NEXT: [[ADD_PTR97_I709]] = getelementptr i16, ptr [[DEST_10_I706]], i64 2
+; CHECK-NEXT: [[SUB99_I710]] = add i64 [[LEN_ADDR_8_I707]], -2
+; CHECK-NEXT: [[TOBOOL100_NOT_I711:%.*]] = icmp eq i64 [[SUB99_I710]], 0
+; CHECK-NEXT: br i1 [[TOBOOL100_NOT_I711]], label %[[FOR_END_LOOPEXIT909]], label %[[DO_BODY93_I705]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK: [[FOR_END_LOOPEXIT909]]:
+; CHECK-NEXT: ret i32 0
+;
+entry:
+ br label %do.body93.i705
+
+do.body93.i705:
+ %dest.10.i706 = phi ptr [ null, %entry ], [ %add.ptr97.i709, %do.body93.i705 ]
+ %len.addr.8.i707 = phi i64 [ 0, %entry ], [ %sub99.i710, %do.body93.i705 ]
+ store i16 %0, ptr %dest.10.i706, align 1
+ %arrayidx96.i708 = getelementptr i16, ptr %dest.10.i706, i64 1
+ store half 0.0, ptr %arrayidx96.i708, align 1
+ %add.ptr97.i709 = getelementptr i16, ptr %dest.10.i706, i64 2
+ %sub99.i710 = add i64 %len.addr.8.i707, -2
+ %tobool100.not.i711 = icmp eq i64 %sub99.i710, 0
+ br i1 %tobool100.not.i711, label %for.end.loopexit909, label %do.body93.i705
+
+for.end.loopexit909:
+ ret i32 0
+}
+;.
+; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
+; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
+; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
+; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
+;.
>From 4562074d3991b2055fa1e5495f273c70ab4989f6 Mon Sep 17 00:00:00 2001
From: Pedro Lobo <pedro.lobo at tecnico.ulisboa.pt>
Date: Sat, 2 Aug 2025 22:56:42 +0100
Subject: [PATCH 2/4] code cleanup
---
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 81f859b903435..e4fc24c98fc18 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -2642,9 +2642,8 @@ namespace {
struct CSEDenseMapInfo {
static bool canHandle(const Instruction *I) {
- return isa<InsertElementInst>(I) || isa<ExtractElementInst>(I) ||
- isa<ShuffleVectorInst>(I) || isa<GetElementPtrInst>(I) ||
- isa<BitCastInst>(I);
+ return isa<InsertElementInst, ExtractElementInst, ShuffleVectorInst,
+ GetElementPtrInst, BitCastInst>(I);
}
static inline Instruction *getEmptyKey() {
>From 8ae7f81f05b0b30301027a43f0b0faf7bc3ee15c Mon Sep 17 00:00:00 2001
From: Pedro Lobo <pedro.lobo at tecnico.ulisboa.pt>
Date: Sat, 2 Aug 2025 22:57:28 +0100
Subject: [PATCH 3/4] test cleanup
---
.../Transforms/LoopVectorize/bitcast-cse.ll | 111 +++++++++++-------
1 file changed, 66 insertions(+), 45 deletions(-)
diff --git a/llvm/test/Transforms/LoopVectorize/bitcast-cse.ll b/llvm/test/Transforms/LoopVectorize/bitcast-cse.ll
index 698a0d071acfe..5564f038bf17e 100644
--- a/llvm/test/Transforms/LoopVectorize/bitcast-cse.ll
+++ b/llvm/test/Transforms/LoopVectorize/bitcast-cse.ll
@@ -1,71 +1,92 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 5
; RUN: opt %s -passes=loop-vectorize -S | FileCheck %s
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
-define i32 @bitcast-cse(i16 %0) {
+define i32 @bitcast-cse(i16 %val, half %fval, ptr %p, i64 %n) {
; CHECK-LABEL: define i32 @bitcast-cse(
-; CHECK-SAME: i16 [[TMP0:%.*]]) {
+; CHECK-SAME: i16 [[VAL:%.*]], half [[FVAL:%.*]], ptr [[P:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 60
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
+; CHECK: [[VECTOR_SCEVCHECK]]:
+; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[N]], -1
+; CHECK-NEXT: [[MUL:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[TMP8]])
+; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i64, i1 } [[MUL]], 0
+; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i64, i1 } [[MUL]], 1
+; CHECK-NEXT: [[TMP9:%.*]] = sub i64 0, [[MUL_RESULT]]
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[P]], i64 [[MUL_RESULT]]
+; CHECK-NEXT: [[TMP11:%.*]] = icmp ult ptr [[TMP10]], [[P]]
+; CHECK-NEXT: [[TMP12:%.*]] = or i1 [[TMP11]], [[MUL_OVERFLOW]]
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P]], i64 2
+; CHECK-NEXT: [[MUL1:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[TMP8]])
+; CHECK-NEXT: [[MUL_RESULT2:%.*]] = extractvalue { i64, i1 } [[MUL1]], 0
+; CHECK-NEXT: [[MUL_OVERFLOW3:%.*]] = extractvalue { i64, i1 } [[MUL1]], 1
+; CHECK-NEXT: [[TMP13:%.*]] = sub i64 0, [[MUL_RESULT2]]
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[MUL_RESULT2]]
+; CHECK-NEXT: [[TMP15:%.*]] = icmp ult ptr [[TMP14]], [[SCEVGEP]]
+; CHECK-NEXT: [[TMP16:%.*]] = or i1 [[TMP15]], [[MUL_OVERFLOW3]]
+; CHECK-NEXT: [[TMP17:%.*]] = or i1 [[TMP12]], [[TMP16]]
+; CHECK-NEXT: br i1 [[TMP17]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
-; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i16> poison, i16 [[TMP0]], i64 0
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 8
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[N_VEC]], 4
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP19]]
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i16> poison, i16 [[VAL]], i64 0
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i16> [[BROADCAST_SPLATINSERT]], <4 x i16> poison, <4 x i32> zeroinitializer
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT4:%.*]] = insertelement <4 x half> poison, half [[FVAL]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT5:%.*]] = shufflevector <4 x half> [[BROADCAST_SPLATINSERT4]], <4 x half> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 16
-; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr null, i64 [[OFFSET_IDX]]
-; CHECK-NEXT: [[NEXT_GEP1:%.*]] = getelementptr i8, ptr null, i64 [[TMP1]]
+; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[P]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT: [[NEXT_GEP1:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP1]]
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[BROADCAST_SPLAT]] to <4 x half>
-; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x half> [[TMP2]], <4 x half> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x half> [[TMP2]], <4 x half> [[BROADCAST_SPLAT5]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <8 x half> [[TMP3]], <8 x half> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
-; CHECK-NEXT: store <8 x half> [[INTERLEAVED_VEC]], ptr [[NEXT_GEP]], align 1
-; CHECK-NEXT: store <8 x half> [[INTERLEAVED_VEC]], ptr [[NEXT_GEP1]], align 1
+; CHECK-NEXT: store <8 x half> [[INTERLEAVED_VEC]], ptr [[NEXT_GEP]], align 2
+; CHECK-NEXT: store <8 x half> [[INTERLEAVED_VEC]], ptr [[NEXT_GEP1]], align 2
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
-; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], -9223372036854775808
-; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-NEXT: [[TMP25:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP25]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: br i1 true, label %[[FOR_END_LOOPEXIT909:.*]], label %[[SCALAR_PH]]
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[END:.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ null, %[[MIDDLE_BLOCK]] ], [ null, %[[ENTRY]] ]
-; CHECK-NEXT: [[BC_RESUME_VAL3:%.*]] = phi i64 [ 0, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
-; CHECK-NEXT: br label %[[DO_BODY93_I705:.*]]
-; CHECK: [[DO_BODY93_I705]]:
-; CHECK-NEXT: [[DEST_10_I706:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[ADD_PTR97_I709:%.*]], %[[DO_BODY93_I705]] ]
-; CHECK-NEXT: [[LEN_ADDR_8_I707:%.*]] = phi i64 [ [[BC_RESUME_VAL3]], %[[SCALAR_PH]] ], [ [[SUB99_I710:%.*]], %[[DO_BODY93_I705]] ]
-; CHECK-NEXT: store i16 [[TMP0]], ptr [[DEST_10_I706]], align 1
-; CHECK-NEXT: [[ARRAYIDX96_I708:%.*]] = getelementptr i16, ptr [[DEST_10_I706]], i64 1
-; CHECK-NEXT: store half 0xH0000, ptr [[ARRAYIDX96_I708]], align 1
-; CHECK-NEXT: [[ADD_PTR97_I709]] = getelementptr i16, ptr [[DEST_10_I706]], i64 2
-; CHECK-NEXT: [[SUB99_I710]] = add i64 [[LEN_ADDR_8_I707]], -2
-; CHECK-NEXT: [[TOBOOL100_NOT_I711:%.*]] = icmp eq i64 [[SUB99_I710]], 0
-; CHECK-NEXT: br i1 [[TOBOOL100_NOT_I711]], label %[[FOR_END_LOOPEXIT909]], label %[[DO_BODY93_I705]], !llvm.loop [[LOOP3:![0-9]+]]
-; CHECK: [[FOR_END_LOOPEXIT909]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP20]], %[[MIDDLE_BLOCK]] ], [ [[P]], %[[ENTRY]] ], [ [[P]], %[[VECTOR_SCEVCHECK]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL8:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[RES:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[RES_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL8]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: store i16 [[VAL]], ptr [[RES]], align 2
+; CHECK-NEXT: [[RES_OFFSET:%.*]] = getelementptr i16, ptr [[RES]], i64 1
+; CHECK-NEXT: store half [[FVAL]], ptr [[RES_OFFSET]], align 2
+; CHECK-NEXT: [[RES_NEXT]] = getelementptr i16, ptr [[RES]], i64 2
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[EXIT_COND]], label %[[END]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK: [[END]]:
; CHECK-NEXT: ret i32 0
;
entry:
- br label %do.body93.i705
+ br label %loop
-do.body93.i705:
- %dest.10.i706 = phi ptr [ null, %entry ], [ %add.ptr97.i709, %do.body93.i705 ]
- %len.addr.8.i707 = phi i64 [ 0, %entry ], [ %sub99.i710, %do.body93.i705 ]
- store i16 %0, ptr %dest.10.i706, align 1
- %arrayidx96.i708 = getelementptr i16, ptr %dest.10.i706, i64 1
- store half 0.0, ptr %arrayidx96.i708, align 1
- %add.ptr97.i709 = getelementptr i16, ptr %dest.10.i706, i64 2
- %sub99.i710 = add i64 %len.addr.8.i707, -2
- %tobool100.not.i711 = icmp eq i64 %sub99.i710, 0
- br i1 %tobool100.not.i711, label %for.end.loopexit909, label %do.body93.i705
+loop:
+ %res = phi ptr [ %p, %entry ], [ %res.next, %loop ]
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ store i16 %val, ptr %res
+ %res.offset = getelementptr i16, ptr %res, i64 1
+ store half %fval, ptr %res.offset
+ %res.next = getelementptr i16, ptr %res, i64 2
+ %iv.next = add i64 %iv, 1
+ %exit.cond = icmp eq i64 %iv.next, %n
+ br i1 %exit.cond, label %end, label %loop
-for.end.loopexit909:
+end:
ret i32 0
}
-;.
-; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
-; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
-; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
-; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
-;.
>From 30df849db2186ea91d6c184a7239ffb9e2fe4d0a Mon Sep 17 00:00:00 2001
From: Pedro Lobo <pedro.lobo at tecnico.ulisboa.pt>
Date: Sun, 3 Aug 2025 09:53:10 +0100
Subject: [PATCH 4/4] move test
---
.../LoopVectorize/{ => X86}/bitcast-cse.ll | 21 +++----------------
1 file changed, 3 insertions(+), 18 deletions(-)
rename llvm/test/Transforms/LoopVectorize/{ => X86}/bitcast-cse.ll (78%)
diff --git a/llvm/test/Transforms/LoopVectorize/bitcast-cse.ll b/llvm/test/Transforms/LoopVectorize/X86/bitcast-cse.ll
similarity index 78%
rename from llvm/test/Transforms/LoopVectorize/bitcast-cse.ll
rename to llvm/test/Transforms/LoopVectorize/X86/bitcast-cse.ll
index 5564f038bf17e..13d710fc063a7 100644
--- a/llvm/test/Transforms/LoopVectorize/bitcast-cse.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/bitcast-cse.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 5
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "^scalar.ph" --version 5
; RUN: opt %s -passes=loop-vectorize -S | FileCheck %s
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
@@ -7,7 +7,7 @@ target triple = "x86_64-unknown-linux-gnu"
define i32 @bitcast-cse(i16 %val, half %fval, ptr %p, i64 %n) {
; CHECK-LABEL: define i32 @bitcast-cse(
; CHECK-SAME: i16 [[VAL:%.*]], half [[FVAL:%.*]], ptr [[P:%.*]], i64 [[N:%.*]]) {
-; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 60
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; CHECK: [[VECTOR_SCEVCHECK]]:
@@ -55,23 +55,8 @@ define i32 @bitcast-cse(i16 %val, half %fval, ptr %p, i64 %n) {
; CHECK-NEXT: br i1 [[TMP25]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[CMP_N]], label %[[END:.*]], label %[[SCALAR_PH]]
+; CHECK-NEXT: br i1 [[CMP_N]], [[END:label %.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP20]], %[[MIDDLE_BLOCK]] ], [ [[P]], %[[ENTRY]] ], [ [[P]], %[[VECTOR_SCEVCHECK]] ]
-; CHECK-NEXT: [[BC_RESUME_VAL8:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
-; CHECK-NEXT: br label %[[LOOP:.*]]
-; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[RES:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[RES_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL8]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: store i16 [[VAL]], ptr [[RES]], align 2
-; CHECK-NEXT: [[RES_OFFSET:%.*]] = getelementptr i16, ptr [[RES]], i64 1
-; CHECK-NEXT: store half [[FVAL]], ptr [[RES_OFFSET]], align 2
-; CHECK-NEXT: [[RES_NEXT]] = getelementptr i16, ptr [[RES]], i64 2
-; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
-; CHECK-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[EXIT_COND]], label %[[END]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
-; CHECK: [[END]]:
-; CHECK-NEXT: ret i32 0
;
entry:
br label %loop
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