[llvm] [ARM] Have custom lowering for ucmp and scmp (PR #149315)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 3 01:51:48 PDT 2025
================
@@ -10614,6 +10624,181 @@ SDValue ARMTargetLowering::LowerFP_TO_BF16(SDValue Op,
return DAG.getBitcast(MVT::i32, Res);
}
+SDValue ARMTargetLowering::LowerSCMP(SDValue Op, SelectionDAG &DAG) const {
+ SDLoc dl(Op);
+ SDValue LHS = Op.getOperand(0);
+ SDValue RHS = Op.getOperand(1);
+
+ // For the ARM assembly pattern:
+ // subs r0, r0, r1 ; subtract RHS from LHS and set flags
+ // movgt r0, #1 ; if LHS > RHS, set result to 1
+ // mvnlt r0, #0 ; if LHS < RHS, set result to -1 (mvn #0 = -1)
+ // ; if LHS == RHS, result remains 0 from the subs
+
+ // Optimization: if RHS is a subtraction against 0, use ADDC instead of SUBC
+ // Check if RHS is (0 - something), and if so use ADDC with LHS + something
+ SDValue SubResult, Flags;
+ bool CanUseAdd = false;
+ SDValue AddOperand;
+
+ // Check if RHS is a subtraction against 0: (0 - X)
+ if (RHS.getOpcode() == ISD::SUB) {
+ SDValue SubLHS = RHS.getOperand(0);
+ SDValue SubRHS = RHS.getOperand(1);
+
+ // Check if it's 0 - X
+ if (isNullConstant(SubLHS)) {
+ // For SCMP: only if X is known to never be INT_MIN (to avoid overflow)
+ if (RHS->getFlags().hasNoSignedWrap() || !DAG.computeKnownBits(SubRHS)
+ .getSignedMinValue()
+ .isMinSignedValue()) {
+ CanUseAdd = true;
----------------
davemgreen wrote:
Maybe remove CanUseAdd and check for if (AddOperand) below? Or maybe just set `Opcode = ARMISD::SUBC;`, then update it to ARMISD::ADDC in the if, so the code for creating AddWithFlags or SubWithFlags can be shared.
https://github.com/llvm/llvm-project/pull/149315
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