[llvm] [RISCV] custom scmp(x, 0) and scmp(0, x) lowering for RVV (PR #151753)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 1 12:40:35 PDT 2025
================
@@ -8223,6 +8225,35 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
case ISD::SADDSAT:
case ISD::SSUBSAT:
return lowerToScalableOp(Op, DAG);
+ case ISD::SCMP: {
+ SDLoc DL(Op);
+ EVT VT = Op->getValueType(0);
+ SDValue LHS = DAG.getFreeze(Op->getOperand(0));
+ SDValue RHS = DAG.getFreeze(Op->getOperand(1));
+ unsigned SEW = VT.getScalarSizeInBits();
+
+ SDValue Shift = DAG.getConstant(SEW-1, DL, VT);
+ SDValue Zero = DAG.getConstant(0, DL, VT);
+ SDValue One = DAG.getConstant(1, DL, VT);
+ SDValue MinusOne = DAG.getAllOnesConstant(DL, VT);
+
+ if (ISD::isConstantSplatVectorAllZeros(RHS.getNode())) {
+ SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, LHS, Shift);
+ if (SEW <= 32) {
+ // scmp(lhs, 0) -> vor.vv(vsra.vi(lhs,SEW-1), vmin.vx(lhs,1))
+ SDValue Min = DAG.getNode(ISD::SMIN, DL, VT, LHS, One);
+ return DAG.getNode(ISD::OR, DL, VT, Sra, Min);
+ }
+ // scmp(lhs, 0) -> vmerge.vi(vmsgt.vi(rhs,0), vsra.vx(lhs,SEW-1), 1)
+ return DAG.getSelectCC(DL, LHS, Zero, Sra, One, ISD::SETGT);
+ } else if (ISD::isConstantSplatVectorAllZeros(LHS.getNode())) {
----------------
topperc wrote:
No else after return.
https://github.com/llvm/llvm-project/pull/151753
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