[llvm] [X86][ARM][RISC-V][XCore][M68K] Invert the low bit to get the inverse predicate (NFC) (PR #151748)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 1 12:30:05 PDT 2025
https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/151748
>From d506a736198cfa9d5e8a3580631c339ae6456400 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Fri, 1 Aug 2025 14:42:41 -0400
Subject: [PATCH 1/8] [X86][ARM] Invert the low bit to get the inverse
predicate (NFC)
Both ARM and x86 defined their predicate in such a way to allow bit twiddling to get inverse predicates
---
llvm/lib/Target/ARM/Utils/ARMBaseInfo.h | 20 ++---------
llvm/lib/Target/X86/X86InstrInfo.cpp | 45 -------------------------
llvm/lib/Target/X86/X86InstrInfo.h | 6 +++-
3 files changed, 8 insertions(+), 63 deletions(-)
diff --git a/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h b/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
index dc4f811e075c6..ebf4eaa122481 100644
--- a/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
+++ b/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
@@ -46,23 +46,9 @@ enum CondCodes { // Meaning (integer) Meaning (floating-point)
};
inline static CondCodes getOppositeCondition(CondCodes CC) {
- switch (CC) {
- default: llvm_unreachable("Unknown condition code");
- case EQ: return NE;
- case NE: return EQ;
- case HS: return LO;
- case LO: return HS;
- case MI: return PL;
- case PL: return MI;
- case VS: return VC;
- case VC: return VS;
- case HI: return LS;
- case LS: return HI;
- case GE: return LT;
- case LT: return GE;
- case GT: return LE;
- case LE: return GT;
- }
+ // To reverse a condition it's necessary to only invert the low bit:
+
+ return static_cast<CondCodes>(static_cast<unsigned>(CC) ^ 0x1);
}
/// getSwappedCondition - assume the flags are set by MI(a,b), return
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index abf365eedec39..6071bbe3da18c 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -3297,51 +3297,6 @@ unsigned X86::getNonNDVariant(unsigned Opc) {
return getNewOpcFromTable(X86ND2NonNDTable, Opc);
}
-/// Return the inverse of the specified condition,
-/// e.g. turning COND_E to COND_NE.
-X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
- switch (CC) {
- default:
- llvm_unreachable("Illegal condition code!");
- case X86::COND_E:
- return X86::COND_NE;
- case X86::COND_NE:
- return X86::COND_E;
- case X86::COND_L:
- return X86::COND_GE;
- case X86::COND_LE:
- return X86::COND_G;
- case X86::COND_G:
- return X86::COND_LE;
- case X86::COND_GE:
- return X86::COND_L;
- case X86::COND_B:
- return X86::COND_AE;
- case X86::COND_BE:
- return X86::COND_A;
- case X86::COND_A:
- return X86::COND_BE;
- case X86::COND_AE:
- return X86::COND_B;
- case X86::COND_S:
- return X86::COND_NS;
- case X86::COND_NS:
- return X86::COND_S;
- case X86::COND_P:
- return X86::COND_NP;
- case X86::COND_NP:
- return X86::COND_P;
- case X86::COND_O:
- return X86::COND_NO;
- case X86::COND_NO:
- return X86::COND_O;
- case X86::COND_NE_OR_P:
- return X86::COND_E_AND_NP;
- case X86::COND_E_AND_NP:
- return X86::COND_NE_OR_P;
- }
-}
-
/// Assuming the flags are set by MI(a,b), return the condition code if we
/// modify the instructions such that flags are set by MI(b,a).
static X86::CondCode getSwappedCondition(X86::CondCode CC) {
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index 9dc5f4b0e086e..6237c6bc989df 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -85,7 +85,11 @@ unsigned getNonNDVariant(unsigned Opc);
/// GetOppositeBranchCondition - Return the inverse of the specified cond,
/// e.g. turning COND_E to COND_NE.
-CondCode GetOppositeBranchCondition(CondCode CC);
+CondCode GetOppositeBranchCondition(CondCode CC) {
+ // To reverse a condition it's necessary to only invert the low bit:
+
+ return static_cast<CondCode>(static_cast<unsigned>(CC) ^ 0x1);
+}
/// Get the VPCMP immediate for the given condition.
unsigned getVPCMPImmForCond(ISD::CondCode CC);
>From 71533c5d2aacb858677eec45d7a1b1ab815dcdf2 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Fri, 1 Aug 2025 14:51:10 -0400
Subject: [PATCH 2/8] Fix concerns
---
llvm/lib/Target/ARM/Utils/ARMBaseInfo.h | 4 +++-
llvm/lib/Target/X86/X86InstrInfo.h | 1 -
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h b/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
index ebf4eaa122481..2af3e8f0eac80 100644
--- a/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
+++ b/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
@@ -47,7 +47,9 @@ enum CondCodes { // Meaning (integer) Meaning (floating-point)
inline static CondCodes getOppositeCondition(CondCodes CC) {
// To reverse a condition it's necessary to only invert the low bit:
-
+ // Note that unlike in AArch64, flipping the bottom bit for AL is not a valid
+ // predicate.
+ assert(CC != AL && "AL has no opposite condition");
return static_cast<CondCodes>(static_cast<unsigned>(CC) ^ 0x1);
}
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index 6237c6bc989df..822134ed327fc 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -87,7 +87,6 @@ unsigned getNonNDVariant(unsigned Opc);
/// e.g. turning COND_E to COND_NE.
CondCode GetOppositeBranchCondition(CondCode CC) {
// To reverse a condition it's necessary to only invert the low bit:
-
return static_cast<CondCode>(static_cast<unsigned>(CC) ^ 0x1);
}
>From 9181c3153ec0a1ed9b0de73a110488a8e90f571b Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Fri, 1 Aug 2025 14:52:47 -0400
Subject: [PATCH 3/8] Add assert for x86
---
llvm/lib/Target/X86/X86InstrInfo.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index 822134ed327fc..fb7011431fb31 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -87,6 +87,7 @@ unsigned getNonNDVariant(unsigned Opc);
/// e.g. turning COND_E to COND_NE.
CondCode GetOppositeBranchCondition(CondCode CC) {
// To reverse a condition it's necessary to only invert the low bit:
+ assert(CC != COND_INVALID && "COND_INVALID has no inverse!");
return static_cast<CondCode>(static_cast<unsigned>(CC) ^ 0x1);
}
>From ce78ca680094bb1cf7bb5bbf1b87c7fcb5619576 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Fri, 1 Aug 2025 15:05:32 -0400
Subject: [PATCH 4/8] Do the same for XCore, RISC_V, and M68k
---
llvm/lib/Target/M68k/M68kInstrInfo.h | 39 ++----------------------
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 19 ------------
llvm/lib/Target/RISCV/RISCVInstrInfo.h | 7 ++++-
llvm/lib/Target/XCore/XCoreInstrInfo.cpp | 12 +++-----
4 files changed, 14 insertions(+), 63 deletions(-)
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.h b/llvm/lib/Target/M68k/M68kInstrInfo.h
index 97615d60caa0b..0124c8c24f82a 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.h
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.h
@@ -56,42 +56,9 @@ enum CondCode {
// mb tag based
static inline M68k::CondCode GetOppositeBranchCondition(M68k::CondCode CC) {
- switch (CC) {
- default:
- llvm_unreachable("Illegal condition code!");
- case M68k::COND_T:
- return M68k::COND_F;
- case M68k::COND_F:
- return M68k::COND_T;
- case M68k::COND_HI:
- return M68k::COND_LS;
- case M68k::COND_LS:
- return M68k::COND_HI;
- case M68k::COND_CC:
- return M68k::COND_CS;
- case M68k::COND_CS:
- return M68k::COND_CC;
- case M68k::COND_NE:
- return M68k::COND_EQ;
- case M68k::COND_EQ:
- return M68k::COND_NE;
- case M68k::COND_VC:
- return M68k::COND_VS;
- case M68k::COND_VS:
- return M68k::COND_VC;
- case M68k::COND_PL:
- return M68k::COND_MI;
- case M68k::COND_MI:
- return M68k::COND_PL;
- case M68k::COND_GE:
- return M68k::COND_LT;
- case M68k::COND_LT:
- return M68k::COND_GE;
- case M68k::COND_GT:
- return M68k::COND_LE;
- case M68k::COND_LE:
- return M68k::COND_GT;
- }
+ // To reverse a condition it's necessary to only invert the low bit:
+ assert(CC != COND_INVALID && "COND_INVALID has no inverse!");
+ return static_cast<CondCode>(static_cast<unsigned>(CC) ^ 0x1);
}
static inline unsigned GetCondBranchFromCond(M68k::CondCode CC) {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 085064eee896a..593092ae7e93c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1128,25 +1128,6 @@ unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC, unsigned SelectOpc) {
}
}
-RISCVCC::CondCode RISCVCC::getOppositeBranchCondition(RISCVCC::CondCode CC) {
- switch (CC) {
- default:
- llvm_unreachable("Unrecognized conditional branch");
- case RISCVCC::COND_EQ:
- return RISCVCC::COND_NE;
- case RISCVCC::COND_NE:
- return RISCVCC::COND_EQ;
- case RISCVCC::COND_LT:
- return RISCVCC::COND_GE;
- case RISCVCC::COND_GE:
- return RISCVCC::COND_LT;
- case RISCVCC::COND_LTU:
- return RISCVCC::COND_GEU;
- case RISCVCC::COND_GEU:
- return RISCVCC::COND_LTU;
- }
-}
-
bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 785c8352d4a5e..284dc15ca8e4a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -44,7 +44,12 @@ enum CondCode {
COND_INVALID
};
-CondCode getOppositeBranchCondition(CondCode);
+CondCode getOppositeBranchCondition(CondCode CC) {
+ // To reverse a condition it's necessary to only invert the low bit:
+ assert(CC != COND_INVALID && "COND_INVALID has no inverse!");
+ return static_cast<CondCode>(static_cast<unsigned>(CC) ^ 0x1);
+}
+
unsigned getBrCond(CondCode CC, unsigned SelectOpc = 0);
} // end of namespace RISCVCC
diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
index 0a86588b6bdb4..ab5617c04d62c 100644
--- a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
+++ b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
@@ -150,13 +150,11 @@ static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
/// GetOppositeBranchCondition - Return the inverse of the specified
/// condition, e.g. turning COND_E to COND_NE.
-static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
-{
- switch (CC) {
- default: llvm_unreachable("Illegal condition code!");
- case XCore::COND_TRUE : return XCore::COND_FALSE;
- case XCore::COND_FALSE : return XCore::COND_TRUE;
- }
+static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) {
+ // To reverse a condition it's necessary to only invert the low bit:
+ assert(CC != XCore::COND_INVALID && "COND_INVALID has no inverse!");
+
+ return static_cast<CondCode>(static_cast<unsigned>(CC) ^ 0x1);
}
/// analyzeBranch - Analyze the branching code at the end of MBB, returning
>From 810150604f2c7324d5f95f068597441c61782d61 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Fri, 1 Aug 2025 15:08:12 -0400
Subject: [PATCH 5/8] Fix compilation errors
---
llvm/lib/Target/M68k/M68kInstrInfo.h | 2 +-
llvm/lib/Target/RISCV/RISCVInstrInfo.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.h b/llvm/lib/Target/M68k/M68kInstrInfo.h
index 0124c8c24f82a..d58444f13efef 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.h
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.h
@@ -57,7 +57,7 @@ enum CondCode {
static inline M68k::CondCode GetOppositeBranchCondition(M68k::CondCode CC) {
// To reverse a condition it's necessary to only invert the low bit:
- assert(CC != COND_INVALID && "COND_INVALID has no inverse!");
+ assert(CC != M86k::COND_INVALID && "COND_INVALID has no inverse!");
return static_cast<CondCode>(static_cast<unsigned>(CC) ^ 0x1);
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 284dc15ca8e4a..024d4a26db592 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -46,7 +46,7 @@ enum CondCode {
CondCode getOppositeBranchCondition(CondCode CC) {
// To reverse a condition it's necessary to only invert the low bit:
- assert(CC != COND_INVALID && "COND_INVALID has no inverse!");
+ assert(CC != RISCVCC::COND_INVALID && "COND_INVALID has no inverse!");
return static_cast<CondCode>(static_cast<unsigned>(CC) ^ 0x1);
}
>From 4f3afca46560388529171450e0ca5e8c0b35b2a2 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Fri, 1 Aug 2025 15:09:46 -0400
Subject: [PATCH 6/8] Update XCoreInstrInfo.cpp
---
llvm/lib/Target/XCore/XCoreInstrInfo.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
index ab5617c04d62c..46a7d0e9487d9 100644
--- a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
+++ b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
@@ -153,7 +153,6 @@ static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) {
// To reverse a condition it's necessary to only invert the low bit:
assert(CC != XCore::COND_INVALID && "COND_INVALID has no inverse!");
-
return static_cast<CondCode>(static_cast<unsigned>(CC) ^ 0x1);
}
>From 08ab62da5ae741e8ae0ac3ab8312a26022436753 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Fri, 1 Aug 2025 15:25:14 -0400
Subject: [PATCH 7/8] Fix compilation errors
---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 6 ++++++
llvm/lib/Target/RISCV/RISCVInstrInfo.h | 6 +-----
llvm/lib/Target/X86/X86InstrInfo.cpp | 8 ++++++++
llvm/lib/Target/X86/X86InstrInfo.h | 6 +-----
llvm/lib/Target/XCore/XCoreInstrInfo.cpp | 2 +-
5 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 593092ae7e93c..616895705058e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1128,6 +1128,12 @@ unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC, unsigned SelectOpc) {
}
}
+RISCVCC::CondCode RISCVCC::getOppositeBranchCondition(RISCVCC::CondCode CC) {
+ // To reverse a condition it's necessary to only invert the low bit:
+ assert(CC != RISCVCC::COND_INVALID && "COND_INVALID has no inverse!");
+ return static_cast<RISCVCC::CondCode>(static_cast<unsigned>(CC) ^ 0x1);
+}
+
bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 024d4a26db592..37fb2557811d2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -44,11 +44,7 @@ enum CondCode {
COND_INVALID
};
-CondCode getOppositeBranchCondition(CondCode CC) {
- // To reverse a condition it's necessary to only invert the low bit:
- assert(CC != RISCVCC::COND_INVALID && "COND_INVALID has no inverse!");
- return static_cast<CondCode>(static_cast<unsigned>(CC) ^ 0x1);
-}
+CondCode getOppositeBranchCondition(CondCode CC);
unsigned getBrCond(CondCode CC, unsigned SelectOpc = 0);
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 6071bbe3da18c..8841e866b0bb4 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -3297,6 +3297,14 @@ unsigned X86::getNonNDVariant(unsigned Opc) {
return getNewOpcFromTable(X86ND2NonNDTable, Opc);
}
+/// Return the inverse of the specified condition,
+/// e.g. turning COND_E to COND_NE.
+X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
+ // To reverse a condition it's necessary to only invert the low bit:
+ assert(CC != COND_INVALID && "COND_INVALID has no inverse!");
+ return static_cast<CondCode>(static_cast<unsigned>(CC) ^ 0x1);
+}
+
/// Assuming the flags are set by MI(a,b), return the condition code if we
/// modify the instructions such that flags are set by MI(b,a).
static X86::CondCode getSwappedCondition(X86::CondCode CC) {
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index fb7011431fb31..9dc5f4b0e086e 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -85,11 +85,7 @@ unsigned getNonNDVariant(unsigned Opc);
/// GetOppositeBranchCondition - Return the inverse of the specified cond,
/// e.g. turning COND_E to COND_NE.
-CondCode GetOppositeBranchCondition(CondCode CC) {
- // To reverse a condition it's necessary to only invert the low bit:
- assert(CC != COND_INVALID && "COND_INVALID has no inverse!");
- return static_cast<CondCode>(static_cast<unsigned>(CC) ^ 0x1);
-}
+CondCode GetOppositeBranchCondition(CondCode CC);
/// Get the VPCMP immediate for the given condition.
unsigned getVPCMPImmForCond(ISD::CondCode CC);
diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
index 46a7d0e9487d9..059805f416c05 100644
--- a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
+++ b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
@@ -153,7 +153,7 @@ static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) {
// To reverse a condition it's necessary to only invert the low bit:
assert(CC != XCore::COND_INVALID && "COND_INVALID has no inverse!");
- return static_cast<CondCode>(static_cast<unsigned>(CC) ^ 0x1);
+ return static_cast<XCore::CondCode>(static_cast<unsigned>(CC) ^ 0x1);
}
/// analyzeBranch - Analyze the branching code at the end of MBB, returning
>From 49c787073324a22a4d7918e89d0cf02c545967e7 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Fri, 1 Aug 2025 15:29:36 -0400
Subject: [PATCH 8/8] Update RISCVInstrInfo.h
---
llvm/lib/Target/RISCV/RISCVInstrInfo.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 37fb2557811d2..785c8352d4a5e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -44,8 +44,7 @@ enum CondCode {
COND_INVALID
};
-CondCode getOppositeBranchCondition(CondCode CC);
-
+CondCode getOppositeBranchCondition(CondCode);
unsigned getBrCond(CondCode CC, unsigned SelectOpc = 0);
} // end of namespace RISCVCC
More information about the llvm-commits
mailing list