[llvm] [SelectionDAG] Move sign pattern check from AArch64 and ARM to general SelectionDAG (PR #151736)

[Craig Topper via llvm-commits]

================
@@ -28972,6 +28972,19 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
                        DAG.getSExtOrTrunc(CC == ISD::SETLT ? N3 : N2, DL, VT));
   }
 
+  // Check for sign pattern (SELECT_CC setgt, iN X, -1, 1, -1) and transform
+  // into (or (ashr X, BW-1), 1).
+  if (CC == ISD::SETGT && N1C && N2C && N3C && N1C->isAllOnes() &&
+      N2C->isOne() && N3C->isAllOnes() &&
+      !TLI.shouldAvoidTransformToShift(CmpOpVT,
+                                       CmpOpVT.getScalarSizeInBits() - 1)) {
+    SDValue ASR = DAG.getNode(
----------------
topperc wrote:

ASR is an ARM instruction name. I don't think it should appear in target independent code. Though I see it is in the code above.

https://github.com/llvm/llvm-project/pull/151736