[llvm] [RISCV] Add intrinsics for strided segment loads with fixed vectors (PR #151611)

[Min-Yih Hsu via llvm-commits]

================
@@ -10959,6 +10966,97 @@ static inline SDValue getVCIXISDNodeVOID(SDValue &Op, SelectionDAG &DAG,
   return DAG.getNode(Type, SDLoc(Op), Op.getValueType(), Operands);
 }
 
+static SDValue
+convertFixedVectorSegLoadIntrinsics(unsigned IntNo, SDValue Op,
----------------
mshockwave wrote:

Done

https://github.com/llvm/llvm-project/pull/151611