[llvm] [RISCV] Implement EmitTargetCodeForMemset for Xqcilsm (PR #151555)

[Craig Topper via llvm-commits]

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@@ -1845,6 +1845,15 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     CurDAG->RemoveDeadNode(Node);
     return;
   }
+  case RISCVISD::QC_SETWMI: {
+    SDValue Chain = Node->getOperand(0);
+    SDVTList VTs = Node->getVTList();
+    SDValue Ops[] = {Node->getOperand(1), Node->getOperand(2),
+                     Node->getOperand(3), Node->getOperand(4), Chain};
+    MachineSDNode *New = CurDAG->getMachineNode(RISCV::QC_SETWMI, DL, VTs, Ops);
+    ReplaceNode(Node, New);
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topperc wrote:

`i32:$rd` also doesn't look right. i32 isn't an operand type. Should be GPR?

https://github.com/llvm/llvm-project/pull/151555