[llvm] 3eda63c - [GVN] Add MemorySSA coverage to tests (NFC)
Antonio Frighetto via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 1 06:12:22 PDT 2025
Author: Antonio Frighetto
Date: 2025-08-01T15:10:58+02:00
New Revision: 3eda63c958bdb8f95547665492264e5d5f28ab35
URL: https://github.com/llvm/llvm-project/commit/3eda63c958bdb8f95547665492264e5d5f28ab35
DIFF: https://github.com/llvm/llvm-project/commit/3eda63c958bdb8f95547665492264e5d5f28ab35.diff
LOG: [GVN] Add MemorySSA coverage to tests (NFC)
Test check lines have been regenerated by ensuring parity between
MemDep and MemorySSA, while migrating towards the latter.
Added:
Modified:
llvm/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll
llvm/test/Transforms/GVN/PRE/pre-after-rle.ll
llvm/test/Transforms/GVN/PRE/rle.ll
Removed:
################################################################################
diff --git a/llvm/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll b/llvm/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll
index d93d521a50ac8..d896a1b164844 100644
--- a/llvm/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll
+++ b/llvm/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll
@@ -1,16 +1,38 @@
-; RUN: opt -aa-pipeline=tbaa,basic-aa -passes=gvn -S < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -aa-pipeline=tbaa,basic-aa -passes=gvn -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-MEMDEP
+; RUN: opt -aa-pipeline=tbaa,basic-aa -passes='gvn<memoryssa>' -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-MEMSSA
target datalayout = "e-p:64:64:64"
; GVN should ignore the store to p1 to see that the load from p is
; fully redundant.
-; CHECK: @yes
-; CHECK: if.then:
-; CHECK-NEXT: store i32 0, ptr %q
-; CHECK-NEXT: ret void
-
define void @yes(i1 %c, ptr %p, ptr %p1, ptr %q) nounwind {
+; CHECK-MEMDEP-LABEL: define void @yes(
+; CHECK-MEMDEP-SAME: i1 [[C:%.*]], ptr [[P:%.*]], ptr [[P1:%.*]], ptr [[Q:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-MEMDEP-NEXT: [[ENTRY:.*:]]
+; CHECK-MEMDEP-NEXT: store i32 0, ptr [[P]], align 4, !tbaa [[TBAA0:![0-9]+]]
+; CHECK-MEMDEP-NEXT: store i32 1, ptr [[P1]], align 4, !tbaa [[TBAA3:![0-9]+]]
+; CHECK-MEMDEP-NEXT: br i1 [[C]], label %[[IF_ELSE:.*]], label %[[IF_THEN:.*]]
+; CHECK-MEMDEP: [[IF_THEN]]:
+; CHECK-MEMDEP-NEXT: store i32 0, ptr [[Q]], align 4
+; CHECK-MEMDEP-NEXT: ret void
+; CHECK-MEMDEP: [[IF_ELSE]]:
+; CHECK-MEMDEP-NEXT: ret void
+;
+; CHECK-MEMSSA-LABEL: define void @yes(
+; CHECK-MEMSSA-SAME: i1 [[C:%.*]], ptr [[P:%.*]], ptr [[P1:%.*]], ptr [[Q:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-MEMSSA-NEXT: [[ENTRY:.*:]]
+; CHECK-MEMSSA-NEXT: store i32 0, ptr [[P]], align 4, !tbaa [[TBAA0:![0-9]+]]
+; CHECK-MEMSSA-NEXT: store i32 1, ptr [[P1]], align 4, !tbaa [[TBAA3:![0-9]+]]
+; CHECK-MEMSSA-NEXT: br i1 [[C]], label %[[IF_ELSE:.*]], label %[[IF_THEN:.*]]
+; CHECK-MEMSSA: [[IF_THEN]]:
+; CHECK-MEMSSA-NEXT: [[T:%.*]] = load i32, ptr [[P]], align 4, !tbaa [[TBAA0]]
+; CHECK-MEMSSA-NEXT: store i32 [[T]], ptr [[Q]], align 4
+; CHECK-MEMSSA-NEXT: ret void
+; CHECK-MEMSSA: [[IF_ELSE]]:
+; CHECK-MEMSSA-NEXT: ret void
+;
entry:
store i32 0, ptr %p, !tbaa !1
store i32 1, ptr %p1, !tbaa !2
@@ -30,16 +52,22 @@ if.else:
; the other type could be unified with the first type, however for now, GVN
; should just be conservative.
-; CHECK: @watch_out_for_type_change
-; CHECK: if.then:
-; CHECK: %t = load i32, ptr %p
-; CHECK: store i32 %t, ptr %q
-; CHECK: ret void
-; CHECK: if.else:
-; CHECK: %u = load i32, ptr %p
-; CHECK: store i32 %u, ptr %q
-
define void @watch_out_for_type_change(i1 %c, ptr %p, ptr %p1, ptr %q) nounwind {
+; CHECK-LABEL: define void @watch_out_for_type_change(
+; CHECK-SAME: i1 [[C:%.*]], ptr [[P:%.*]], ptr [[P1:%.*]], ptr [[Q:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: store i32 0, ptr [[P]], align 4, !tbaa [[TBAA0:![0-9]+]]
+; CHECK-NEXT: store i32 1, ptr [[P1]], align 4, !tbaa [[TBAA3:![0-9]+]]
+; CHECK-NEXT: br i1 [[C]], label %[[IF_ELSE:.*]], label %[[IF_THEN:.*]]
+; CHECK: [[IF_THEN]]:
+; CHECK-NEXT: [[T:%.*]] = load i32, ptr [[P]], align 4, !tbaa [[TBAA5:![0-9]+]]
+; CHECK-NEXT: store i32 [[T]], ptr [[Q]], align 4
+; CHECK-NEXT: ret void
+; CHECK: [[IF_ELSE]]:
+; CHECK-NEXT: [[U:%.*]] = load i32, ptr [[P]], align 4, !tbaa [[TBAA8:![0-9]+]]
+; CHECK-NEXT: store i32 [[U]], ptr [[Q]], align 4
+; CHECK-NEXT: ret void
+;
entry:
store i32 0, ptr %p, !tbaa !1
store i32 1, ptr %p1, !tbaa !2
@@ -59,15 +87,36 @@ if.else:
; As before, but the types are swapped. This time GVN does managed to
; eliminate one of the loads before noticing the type mismatch.
-; CHECK: @watch_out_for_another_type_change
-; CHECK: if.then:
-; CHECK: store i32 0, ptr %q
-; CHECK: ret void
-; CHECK: if.else:
-; CHECK: %u = load i32, ptr %p
-; CHECK: store i32 %u, ptr %q
-
define void @watch_out_for_another_type_change(i1 %c, ptr %p, ptr %p1, ptr %q) nounwind {
+; CHECK-MEMDEP-LABEL: define void @watch_out_for_another_type_change(
+; CHECK-MEMDEP-SAME: i1 [[C:%.*]], ptr [[P:%.*]], ptr [[P1:%.*]], ptr [[Q:%.*]]) #[[ATTR0]] {
+; CHECK-MEMDEP-NEXT: [[ENTRY:.*:]]
+; CHECK-MEMDEP-NEXT: store i32 0, ptr [[P]], align 4, !tbaa [[TBAA0]]
+; CHECK-MEMDEP-NEXT: store i32 1, ptr [[P1]], align 4, !tbaa [[TBAA3]]
+; CHECK-MEMDEP-NEXT: br i1 [[C]], label %[[IF_ELSE:.*]], label %[[IF_THEN:.*]]
+; CHECK-MEMDEP: [[IF_THEN]]:
+; CHECK-MEMDEP-NEXT: store i32 0, ptr [[Q]], align 4
+; CHECK-MEMDEP-NEXT: ret void
+; CHECK-MEMDEP: [[IF_ELSE]]:
+; CHECK-MEMDEP-NEXT: [[U:%.*]] = load i32, ptr [[P]], align 4, !tbaa [[TBAA5]]
+; CHECK-MEMDEP-NEXT: store i32 [[U]], ptr [[Q]], align 4
+; CHECK-MEMDEP-NEXT: ret void
+;
+; CHECK-MEMSSA-LABEL: define void @watch_out_for_another_type_change(
+; CHECK-MEMSSA-SAME: i1 [[C:%.*]], ptr [[P:%.*]], ptr [[P1:%.*]], ptr [[Q:%.*]]) #[[ATTR0]] {
+; CHECK-MEMSSA-NEXT: [[ENTRY:.*:]]
+; CHECK-MEMSSA-NEXT: store i32 0, ptr [[P]], align 4, !tbaa [[TBAA0]]
+; CHECK-MEMSSA-NEXT: store i32 1, ptr [[P1]], align 4, !tbaa [[TBAA3]]
+; CHECK-MEMSSA-NEXT: br i1 [[C]], label %[[IF_ELSE:.*]], label %[[IF_THEN:.*]]
+; CHECK-MEMSSA: [[IF_THEN]]:
+; CHECK-MEMSSA-NEXT: [[T:%.*]] = load i32, ptr [[P]], align 4, !tbaa [[TBAA8]]
+; CHECK-MEMSSA-NEXT: store i32 [[T]], ptr [[Q]], align 4
+; CHECK-MEMSSA-NEXT: ret void
+; CHECK-MEMSSA: [[IF_ELSE]]:
+; CHECK-MEMSSA-NEXT: [[U:%.*]] = load i32, ptr [[P]], align 4, !tbaa [[TBAA5]]
+; CHECK-MEMSSA-NEXT: store i32 [[U]], ptr [[Q]], align 4
+; CHECK-MEMSSA-NEXT: ret void
+;
entry:
store i32 0, ptr %p, !tbaa !1
store i32 1, ptr %p1, !tbaa !2
@@ -94,3 +143,26 @@ if.else:
!7 = !{!"outer space", !9}
!8 = !{!"brick red", !5}
!9 = !{!"observable universe"}
+;.
+; CHECK-MEMDEP: [[TBAA0]] = !{[[META1:![0-9]+]], [[META1]], i64 0}
+; CHECK-MEMDEP: [[META1]] = !{!"red", [[META2:![0-9]+]]}
+; CHECK-MEMDEP: [[META2]] = !{}
+; CHECK-MEMDEP: [[TBAA3]] = !{[[META4:![0-9]+]], [[META4]], i64 0}
+; CHECK-MEMDEP: [[META4]] = !{!"blu", [[META2]]}
+; CHECK-MEMDEP: [[TBAA5]] = !{[[META6:![0-9]+]], [[META6]], i64 0}
+; CHECK-MEMDEP: [[META6]] = !{!"outer space", [[META7:![0-9]+]]}
+; CHECK-MEMDEP: [[META7]] = !{!"observable universe"}
+; CHECK-MEMDEP: [[TBAA8]] = !{[[META9:![0-9]+]], [[META9]], i64 0}
+; CHECK-MEMDEP: [[META9]] = !{!"brick red", [[META1]]}
+;.
+; CHECK-MEMSSA: [[TBAA0]] = !{[[META1:![0-9]+]], [[META1]], i64 0}
+; CHECK-MEMSSA: [[META1]] = !{!"red", [[META2:![0-9]+]]}
+; CHECK-MEMSSA: [[META2]] = !{}
+; CHECK-MEMSSA: [[TBAA3]] = !{[[META4:![0-9]+]], [[META4]], i64 0}
+; CHECK-MEMSSA: [[META4]] = !{!"blu", [[META2]]}
+; CHECK-MEMSSA: [[TBAA5]] = !{[[META6:![0-9]+]], [[META6]], i64 0}
+; CHECK-MEMSSA: [[META6]] = !{!"outer space", [[META7:![0-9]+]]}
+; CHECK-MEMSSA: [[META7]] = !{!"observable universe"}
+; CHECK-MEMSSA: [[TBAA8]] = !{[[META9:![0-9]+]], [[META9]], i64 0}
+; CHECK-MEMSSA: [[META9]] = !{!"brick red", [[META1]]}
+;.
diff --git a/llvm/test/Transforms/GVN/PRE/pre-after-rle.ll b/llvm/test/Transforms/GVN/PRE/pre-after-rle.ll
index be3663c04fa70..b18ad5dae4633 100644
--- a/llvm/test/Transforms/GVN/PRE/pre-after-rle.ll
+++ b/llvm/test/Transforms/GVN/PRE/pre-after-rle.ll
@@ -1,30 +1,52 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes='require<phi-values>,gvn' -S < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -passes='require<phi-values>,gvn' -S < %s | FileCheck %s --check-prefixes=CHECK-MEMDEP
+; RUN: opt -passes='require<phi-values>,gvn<memoryssa>' -S < %s | FileCheck %s --check-prefixes=CHECK-MEMSSA
declare noalias ptr @malloc(i64)
; Detecting that %s is fully redundant should let us detect that %w is partially
; redundant.
define void @fn1(ptr noalias %start, ptr %width, i32 %h) {
-; CHECK-LABEL: @fn1(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CALL:%.*]] = tail call noalias ptr @malloc(i64 1024)
-; CHECK-NEXT: store ptr [[CALL]], ptr [[START:%.*]], align 8
-; CHECK-NEXT: br label [[PREHEADER:%.*]]
-; CHECK: preheader:
-; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 1, [[H:%.*]]
-; CHECK-NEXT: br i1 [[CMP]], label [[PREHEADER_BODY_CRIT_EDGE:%.*]], label [[EXIT:%.*]]
-; CHECK: preheader.body_crit_edge:
-; CHECK-NEXT: [[W_PRE:%.*]] = load i32, ptr [[WIDTH:%.*]], align 8
-; CHECK-NEXT: br label [[BODY:%.*]]
-; CHECK: body:
-; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[PREHEADER_BODY_CRIT_EDGE]] ], [ [[J_NEXT:%.*]], [[BODY]] ]
-; CHECK-NEXT: store i32 0, ptr [[CALL]], align 4
-; CHECK-NEXT: [[J_NEXT]] = add nuw nsw i32 [[J]], 1
-; CHECK-NEXT: [[CMP3:%.*]] = icmp slt i32 [[J_NEXT]], [[W_PRE]]
-; CHECK-NEXT: br i1 [[CMP3]], label [[BODY]], label [[PREHEADER]]
-; CHECK: exit:
-; CHECK-NEXT: ret void
+; CHECK-MEMDEP-LABEL: define void @fn1(
+; CHECK-MEMDEP-SAME: ptr noalias [[START:%.*]], ptr [[WIDTH:%.*]], i32 [[H:%.*]]) {
+; CHECK-MEMDEP-NEXT: [[ENTRY:.*:]]
+; CHECK-MEMDEP-NEXT: [[CALL:%.*]] = tail call noalias ptr @malloc(i64 1024)
+; CHECK-MEMDEP-NEXT: store ptr [[CALL]], ptr [[START]], align 8
+; CHECK-MEMDEP-NEXT: br label %[[PREHEADER:.*]]
+; CHECK-MEMDEP: [[PREHEADER]]:
+; CHECK-MEMDEP-NEXT: [[CMP:%.*]] = icmp slt i32 1, [[H]]
+; CHECK-MEMDEP-NEXT: br i1 [[CMP]], label %[[PREHEADER_BODY_CRIT_EDGE:.*]], label %[[EXIT:.*]]
+; CHECK-MEMDEP: [[PREHEADER_BODY_CRIT_EDGE]]:
+; CHECK-MEMDEP-NEXT: [[W_PRE:%.*]] = load i32, ptr [[WIDTH]], align 8
+; CHECK-MEMDEP-NEXT: br label %[[BODY:.*]]
+; CHECK-MEMDEP: [[BODY]]:
+; CHECK-MEMDEP-NEXT: [[J:%.*]] = phi i32 [ 0, %[[PREHEADER_BODY_CRIT_EDGE]] ], [ [[J_NEXT:%.*]], %[[BODY]] ]
+; CHECK-MEMDEP-NEXT: store i32 0, ptr [[CALL]], align 4
+; CHECK-MEMDEP-NEXT: [[J_NEXT]] = add nuw nsw i32 [[J]], 1
+; CHECK-MEMDEP-NEXT: [[CMP3:%.*]] = icmp slt i32 [[J_NEXT]], [[W_PRE]]
+; CHECK-MEMDEP-NEXT: br i1 [[CMP3]], label %[[BODY]], label %[[PREHEADER]]
+; CHECK-MEMDEP: [[EXIT]]:
+; CHECK-MEMDEP-NEXT: ret void
+;
+; CHECK-MEMSSA-LABEL: define void @fn1(
+; CHECK-MEMSSA-SAME: ptr noalias [[START:%.*]], ptr [[WIDTH:%.*]], i32 [[H:%.*]]) {
+; CHECK-MEMSSA-NEXT: [[ENTRY:.*:]]
+; CHECK-MEMSSA-NEXT: [[CALL:%.*]] = tail call noalias ptr @malloc(i64 1024)
+; CHECK-MEMSSA-NEXT: store ptr [[CALL]], ptr [[START]], align 8
+; CHECK-MEMSSA-NEXT: br label %[[PREHEADER:.*]]
+; CHECK-MEMSSA: [[PREHEADER]]:
+; CHECK-MEMSSA-NEXT: [[CMP:%.*]] = icmp slt i32 1, [[H]]
+; CHECK-MEMSSA-NEXT: br i1 [[CMP]], label %[[BODY:.*]], label %[[EXIT:.*]]
+; CHECK-MEMSSA: [[BODY]]:
+; CHECK-MEMSSA-NEXT: [[J:%.*]] = phi i32 [ 0, %[[PREHEADER]] ], [ [[J_NEXT:%.*]], %[[BODY]] ]
+; CHECK-MEMSSA-NEXT: [[S:%.*]] = load ptr, ptr [[START]], align 8
+; CHECK-MEMSSA-NEXT: store i32 0, ptr [[S]], align 4
+; CHECK-MEMSSA-NEXT: [[J_NEXT]] = add nuw nsw i32 [[J]], 1
+; CHECK-MEMSSA-NEXT: [[W:%.*]] = load i32, ptr [[WIDTH]], align 8
+; CHECK-MEMSSA-NEXT: [[CMP3:%.*]] = icmp slt i32 [[J_NEXT]], [[W]]
+; CHECK-MEMSSA-NEXT: br i1 [[CMP3]], label %[[BODY]], label %[[PREHEADER]]
+; CHECK-MEMSSA: [[EXIT]]:
+; CHECK-MEMSSA-NEXT: ret void
;
entry:
%call = tail call noalias ptr @malloc(i64 1024)
@@ -52,33 +74,61 @@ exit:
; %w is partially redundant requires alias analysis that can analyze those
; values.
define void @fn2(ptr noalias %start, ptr %width, i32 %h, i32 %arg) {
-; CHECK-LABEL: @fn2(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CALL:%.*]] = tail call noalias ptr @malloc(i64 1024)
-; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ARG:%.*]], 0
-; CHECK-NEXT: br i1 [[CMP1]], label [[IF:%.*]], label [[ELSE:%.*]]
-; CHECK: if:
-; CHECK-NEXT: store ptr [[CALL]], ptr [[START:%.*]], align 8
-; CHECK-NEXT: br label [[PREHEADER:%.*]]
-; CHECK: else:
-; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[CALL]], i32 [[ARG]]
-; CHECK-NEXT: store ptr [[GEP]], ptr [[START]], align 8
-; CHECK-NEXT: br label [[PREHEADER]]
-; CHECK: preheader:
-; CHECK-NEXT: [[S:%.*]] = phi ptr [ [[S]], [[BODY:%.*]] ], [ [[GEP]], [[ELSE]] ], [ [[CALL]], [[IF]] ]
-; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 1, [[H:%.*]]
-; CHECK-NEXT: br i1 [[CMP]], label [[PREHEADER_BODY_CRIT_EDGE:%.*]], label [[EXIT:%.*]]
-; CHECK: preheader.body_crit_edge:
-; CHECK-NEXT: [[W_PRE:%.*]] = load i32, ptr [[WIDTH:%.*]], align 8
-; CHECK-NEXT: br label [[BODY]]
-; CHECK: body:
-; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[PREHEADER_BODY_CRIT_EDGE]] ], [ [[J_NEXT:%.*]], [[BODY]] ]
-; CHECK-NEXT: store i32 0, ptr [[S]], align 4
-; CHECK-NEXT: [[J_NEXT]] = add nuw nsw i32 [[J]], 1
-; CHECK-NEXT: [[CMP3:%.*]] = icmp slt i32 [[J_NEXT]], [[W_PRE]]
-; CHECK-NEXT: br i1 [[CMP3]], label [[BODY]], label [[PREHEADER]]
-; CHECK: exit:
-; CHECK-NEXT: ret void
+; CHECK-MEMDEP-LABEL: define void @fn2(
+; CHECK-MEMDEP-SAME: ptr noalias [[START:%.*]], ptr [[WIDTH:%.*]], i32 [[H:%.*]], i32 [[ARG:%.*]]) {
+; CHECK-MEMDEP-NEXT: [[ENTRY:.*:]]
+; CHECK-MEMDEP-NEXT: [[CALL:%.*]] = tail call noalias ptr @malloc(i64 1024)
+; CHECK-MEMDEP-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ARG]], 0
+; CHECK-MEMDEP-NEXT: br i1 [[CMP1]], label %[[IF:.*]], label %[[ELSE:.*]]
+; CHECK-MEMDEP: [[IF]]:
+; CHECK-MEMDEP-NEXT: store ptr [[CALL]], ptr [[START]], align 8
+; CHECK-MEMDEP-NEXT: br label %[[PREHEADER:.*]]
+; CHECK-MEMDEP: [[ELSE]]:
+; CHECK-MEMDEP-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[CALL]], i32 [[ARG]]
+; CHECK-MEMDEP-NEXT: store ptr [[GEP]], ptr [[START]], align 8
+; CHECK-MEMDEP-NEXT: br label %[[PREHEADER]]
+; CHECK-MEMDEP: [[PREHEADER]]:
+; CHECK-MEMDEP-NEXT: [[S:%.*]] = phi ptr [ [[S]], %[[BODY:.*]] ], [ [[GEP]], %[[ELSE]] ], [ [[CALL]], %[[IF]] ]
+; CHECK-MEMDEP-NEXT: [[CMP:%.*]] = icmp slt i32 1, [[H]]
+; CHECK-MEMDEP-NEXT: br i1 [[CMP]], label %[[PREHEADER_BODY_CRIT_EDGE:.*]], label %[[EXIT:.*]]
+; CHECK-MEMDEP: [[PREHEADER_BODY_CRIT_EDGE]]:
+; CHECK-MEMDEP-NEXT: [[W_PRE:%.*]] = load i32, ptr [[WIDTH]], align 8
+; CHECK-MEMDEP-NEXT: br label %[[BODY]]
+; CHECK-MEMDEP: [[BODY]]:
+; CHECK-MEMDEP-NEXT: [[J:%.*]] = phi i32 [ 0, %[[PREHEADER_BODY_CRIT_EDGE]] ], [ [[J_NEXT:%.*]], %[[BODY]] ]
+; CHECK-MEMDEP-NEXT: store i32 0, ptr [[S]], align 4
+; CHECK-MEMDEP-NEXT: [[J_NEXT]] = add nuw nsw i32 [[J]], 1
+; CHECK-MEMDEP-NEXT: [[CMP3:%.*]] = icmp slt i32 [[J_NEXT]], [[W_PRE]]
+; CHECK-MEMDEP-NEXT: br i1 [[CMP3]], label %[[BODY]], label %[[PREHEADER]]
+; CHECK-MEMDEP: [[EXIT]]:
+; CHECK-MEMDEP-NEXT: ret void
+;
+; CHECK-MEMSSA-LABEL: define void @fn2(
+; CHECK-MEMSSA-SAME: ptr noalias [[START:%.*]], ptr [[WIDTH:%.*]], i32 [[H:%.*]], i32 [[ARG:%.*]]) {
+; CHECK-MEMSSA-NEXT: [[ENTRY:.*:]]
+; CHECK-MEMSSA-NEXT: [[CALL:%.*]] = tail call noalias ptr @malloc(i64 1024)
+; CHECK-MEMSSA-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ARG]], 0
+; CHECK-MEMSSA-NEXT: br i1 [[CMP1]], label %[[IF:.*]], label %[[ELSE:.*]]
+; CHECK-MEMSSA: [[IF]]:
+; CHECK-MEMSSA-NEXT: store ptr [[CALL]], ptr [[START]], align 8
+; CHECK-MEMSSA-NEXT: br label %[[PREHEADER:.*]]
+; CHECK-MEMSSA: [[ELSE]]:
+; CHECK-MEMSSA-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[CALL]], i32 [[ARG]]
+; CHECK-MEMSSA-NEXT: store ptr [[GEP]], ptr [[START]], align 8
+; CHECK-MEMSSA-NEXT: br label %[[PREHEADER]]
+; CHECK-MEMSSA: [[PREHEADER]]:
+; CHECK-MEMSSA-NEXT: [[CMP:%.*]] = icmp slt i32 1, [[H]]
+; CHECK-MEMSSA-NEXT: br i1 [[CMP]], label %[[BODY:.*]], label %[[EXIT:.*]]
+; CHECK-MEMSSA: [[BODY]]:
+; CHECK-MEMSSA-NEXT: [[J:%.*]] = phi i32 [ 0, %[[PREHEADER]] ], [ [[J_NEXT:%.*]], %[[BODY]] ]
+; CHECK-MEMSSA-NEXT: [[S:%.*]] = load ptr, ptr [[START]], align 8
+; CHECK-MEMSSA-NEXT: store i32 0, ptr [[S]], align 4
+; CHECK-MEMSSA-NEXT: [[J_NEXT]] = add nuw nsw i32 [[J]], 1
+; CHECK-MEMSSA-NEXT: [[W:%.*]] = load i32, ptr [[WIDTH]], align 8
+; CHECK-MEMSSA-NEXT: [[CMP3:%.*]] = icmp slt i32 [[J_NEXT]], [[W]]
+; CHECK-MEMSSA-NEXT: br i1 [[CMP3]], label %[[BODY]], label %[[PREHEADER]]
+; CHECK-MEMSSA: [[EXIT]]:
+; CHECK-MEMSSA-NEXT: ret void
;
entry:
%call = tail call noalias ptr @malloc(i64 1024)
diff --git a/llvm/test/Transforms/GVN/PRE/rle.ll b/llvm/test/Transforms/GVN/PRE/rle.ll
index c81c1fe1c982f..e495163fa43cd 100644
--- a/llvm/test/Transforms/GVN/PRE/rle.ll
+++ b/llvm/test/Transforms/GVN/PRE/rle.ll
@@ -1,12 +1,32 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -data-layout="e-p:32:32:32-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-n8:16:32" -passes=gvn,dce -enable-split-backedge-in-load-pre -S | FileCheck %s --check-prefixes=CHECK,LE
-; RUN: opt < %s -data-layout="E-p:32:32:32-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-n32" -passes=gvn,dce -enable-split-backedge-in-load-pre -S | FileCheck %s --check-prefixes=CHECK,BE
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt < %s -data-layout="e-p:32:32:32-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-n8:16:32" -passes=gvn,dce -enable-split-backedge-in-load-pre -S | FileCheck %s --check-prefixes=CHECK,LE,LE-MEMDEP
+; RUN: opt < %s -data-layout="e-p:32:32:32-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-n8:16:32" -passes='gvn<memoryssa>',dce -enable-split-backedge-in-load-pre -S | FileCheck %s --check-prefixes=CHECK,LE,LE-MEMSSA
+; RUN: opt < %s -data-layout="E-p:32:32:32-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-n32" -passes=gvn,dce -enable-split-backedge-in-load-pre -S | FileCheck %s --check-prefixes=CHECK,BE,BE-MEMDEP
+; RUN: opt < %s -data-layout="E-p:32:32:32-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-n32" -passes='gvn<memoryssa>',dce -enable-split-backedge-in-load-pre -S | FileCheck %s --check-prefixes=CHECK,BE,BE-MEMSSA
;; Trivial RLE test.
define i32 @test0(i32 %V, ptr %P) {
-; CHECK-LABEL: @test0(
-; CHECK-NEXT: store i32 [[V:%.*]], ptr [[P:%.*]], align 4
-; CHECK-NEXT: ret i32 [[V]]
+; LE-MEMDEP-LABEL: define i32 @test0(
+; LE-MEMDEP-SAME: i32 [[V:%.*]], ptr [[P:%.*]]) {
+; LE-MEMDEP-NEXT: store i32 [[V]], ptr [[P]], align 4
+; LE-MEMDEP-NEXT: ret i32 [[V]]
+;
+; LE-MEMSSA-LABEL: define i32 @test0(
+; LE-MEMSSA-SAME: i32 [[V:%.*]], ptr [[P:%.*]]) {
+; LE-MEMSSA-NEXT: store i32 [[V]], ptr [[P]], align 4
+; LE-MEMSSA-NEXT: [[A:%.*]] = load i32, ptr [[P]], align 4
+; LE-MEMSSA-NEXT: ret i32 [[A]]
+;
+; BE-MEMDEP-LABEL: define i32 @test0(
+; BE-MEMDEP-SAME: i32 [[V:%.*]], ptr [[P:%.*]]) {
+; BE-MEMDEP-NEXT: store i32 [[V]], ptr [[P]], align 4
+; BE-MEMDEP-NEXT: ret i32 [[V]]
+;
+; BE-MEMSSA-LABEL: define i32 @test0(
+; BE-MEMSSA-SAME: i32 [[V:%.*]], ptr [[P:%.*]]) {
+; BE-MEMSSA-NEXT: store i32 [[V]], ptr [[P]], align 4
+; BE-MEMSSA-NEXT: [[A:%.*]] = load i32, ptr [[P]], align 4
+; BE-MEMSSA-NEXT: ret i32 [[A]]
;
store i32 %V, ptr %P
@@ -21,8 +41,9 @@ define i32 @test0(i32 %V, ptr %P) {
;; PR5016
define i8 @crash0({i32, i32} %A, ptr %P) {
-; CHECK-LABEL: @crash0(
-; CHECK-NEXT: store { i32, i32 } [[A:%.*]], ptr [[P:%.*]], align 4
+; CHECK-LABEL: define i8 @crash0(
+; CHECK-SAME: { i32, i32 } [[A:%.*]], ptr [[P:%.*]]) {
+; CHECK-NEXT: store { i32, i32 } [[A]], ptr [[P]], align 4
; CHECK-NEXT: [[Y:%.*]] = load i8, ptr [[P]], align 1
; CHECK-NEXT: ret i8 [[Y]]
;
@@ -34,7 +55,7 @@ define i8 @crash0({i32, i32} %A, ptr %P) {
;; No PR filed, crashed in CaptureTracker.
declare void @helper()
define void @crash1() {
-; CHECK-LABEL: @crash1(
+; CHECK-LABEL: define void @crash1() {
; CHECK-NEXT: tail call void @llvm.memcpy.p0.p0.i64(ptr undef, ptr undef, i64 undef, i1 false) #[[ATTR3:[0-9]+]]
; CHECK-NEXT: ret void
;
@@ -52,10 +73,29 @@ define void @crash1() {
;; i32 -> f32 forwarding.
define float @coerce_mustalias1(i32 %V, ptr %P) {
-; CHECK-LABEL: @coerce_mustalias1(
-; CHECK-NEXT: store i32 [[V:%.*]], ptr [[P:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[V]] to float
-; CHECK-NEXT: ret float [[TMP1]]
+; LE-MEMDEP-LABEL: define float @coerce_mustalias1(
+; LE-MEMDEP-SAME: i32 [[V:%.*]], ptr [[P:%.*]]) {
+; LE-MEMDEP-NEXT: store i32 [[V]], ptr [[P]], align 4
+; LE-MEMDEP-NEXT: [[TMP1:%.*]] = bitcast i32 [[V]] to float
+; LE-MEMDEP-NEXT: ret float [[TMP1]]
+;
+; LE-MEMSSA-LABEL: define float @coerce_mustalias1(
+; LE-MEMSSA-SAME: i32 [[V:%.*]], ptr [[P:%.*]]) {
+; LE-MEMSSA-NEXT: store i32 [[V]], ptr [[P]], align 4
+; LE-MEMSSA-NEXT: [[A:%.*]] = load float, ptr [[P]], align 4
+; LE-MEMSSA-NEXT: ret float [[A]]
+;
+; BE-MEMDEP-LABEL: define float @coerce_mustalias1(
+; BE-MEMDEP-SAME: i32 [[V:%.*]], ptr [[P:%.*]]) {
+; BE-MEMDEP-NEXT: store i32 [[V]], ptr [[P]], align 4
+; BE-MEMDEP-NEXT: [[TMP1:%.*]] = bitcast i32 [[V]] to float
+; BE-MEMDEP-NEXT: ret float [[TMP1]]
+;
+; BE-MEMSSA-LABEL: define float @coerce_mustalias1(
+; BE-MEMSSA-SAME: i32 [[V:%.*]], ptr [[P:%.*]]) {
+; BE-MEMSSA-NEXT: store i32 [[V]], ptr [[P]], align 4
+; BE-MEMSSA-NEXT: [[A:%.*]] = load float, ptr [[P]], align 4
+; BE-MEMSSA-NEXT: ret float [[A]]
;
store i32 %V, ptr %P
@@ -66,11 +106,31 @@ define float @coerce_mustalias1(i32 %V, ptr %P) {
;; ptr -> float forwarding.
define float @coerce_mustalias2(ptr %V, ptr %P) {
-; CHECK-LABEL: @coerce_mustalias2(
-; CHECK-NEXT: store ptr [[V:%.*]], ptr [[P:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[V]] to i32
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[TMP1]] to float
-; CHECK-NEXT: ret float [[TMP2]]
+; LE-MEMDEP-LABEL: define float @coerce_mustalias2(
+; LE-MEMDEP-SAME: ptr [[V:%.*]], ptr [[P:%.*]]) {
+; LE-MEMDEP-NEXT: store ptr [[V]], ptr [[P]], align 4
+; LE-MEMDEP-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[V]] to i32
+; LE-MEMDEP-NEXT: [[TMP2:%.*]] = bitcast i32 [[TMP1]] to float
+; LE-MEMDEP-NEXT: ret float [[TMP2]]
+;
+; LE-MEMSSA-LABEL: define float @coerce_mustalias2(
+; LE-MEMSSA-SAME: ptr [[V:%.*]], ptr [[P:%.*]]) {
+; LE-MEMSSA-NEXT: store ptr [[V]], ptr [[P]], align 4
+; LE-MEMSSA-NEXT: [[A:%.*]] = load float, ptr [[P]], align 4
+; LE-MEMSSA-NEXT: ret float [[A]]
+;
+; BE-MEMDEP-LABEL: define float @coerce_mustalias2(
+; BE-MEMDEP-SAME: ptr [[V:%.*]], ptr [[P:%.*]]) {
+; BE-MEMDEP-NEXT: store ptr [[V]], ptr [[P]], align 4
+; BE-MEMDEP-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[V]] to i32
+; BE-MEMDEP-NEXT: [[TMP2:%.*]] = bitcast i32 [[TMP1]] to float
+; BE-MEMDEP-NEXT: ret float [[TMP2]]
+;
+; BE-MEMSSA-LABEL: define float @coerce_mustalias2(
+; BE-MEMSSA-SAME: ptr [[V:%.*]], ptr [[P:%.*]]) {
+; BE-MEMSSA-NEXT: store ptr [[V]], ptr [[P]], align 4
+; BE-MEMSSA-NEXT: [[A:%.*]] = load float, ptr [[P]], align 4
+; BE-MEMSSA-NEXT: ret float [[A]]
;
store ptr %V, ptr %P
@@ -81,11 +141,31 @@ define float @coerce_mustalias2(ptr %V, ptr %P) {
;; float -> ptr forwarding.
define ptr @coerce_mustalias3(float %V, ptr %P) {
-; CHECK-LABEL: @coerce_mustalias3(
-; CHECK-NEXT: store float [[V:%.*]], ptr [[P:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[V]] to i32
-; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr
-; CHECK-NEXT: ret ptr [[TMP2]]
+; LE-MEMDEP-LABEL: define ptr @coerce_mustalias3(
+; LE-MEMDEP-SAME: float [[V:%.*]], ptr [[P:%.*]]) {
+; LE-MEMDEP-NEXT: store float [[V]], ptr [[P]], align 4
+; LE-MEMDEP-NEXT: [[TMP1:%.*]] = bitcast float [[V]] to i32
+; LE-MEMDEP-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr
+; LE-MEMDEP-NEXT: ret ptr [[TMP2]]
+;
+; LE-MEMSSA-LABEL: define ptr @coerce_mustalias3(
+; LE-MEMSSA-SAME: float [[V:%.*]], ptr [[P:%.*]]) {
+; LE-MEMSSA-NEXT: store float [[V]], ptr [[P]], align 4
+; LE-MEMSSA-NEXT: [[A:%.*]] = load ptr, ptr [[P]], align 4
+; LE-MEMSSA-NEXT: ret ptr [[A]]
+;
+; BE-MEMDEP-LABEL: define ptr @coerce_mustalias3(
+; BE-MEMDEP-SAME: float [[V:%.*]], ptr [[P:%.*]]) {
+; BE-MEMDEP-NEXT: store float [[V]], ptr [[P]], align 4
+; BE-MEMDEP-NEXT: [[TMP1:%.*]] = bitcast float [[V]] to i32
+; BE-MEMDEP-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr
+; BE-MEMDEP-NEXT: ret ptr [[TMP2]]
+;
+; BE-MEMSSA-LABEL: define ptr @coerce_mustalias3(
+; BE-MEMSSA-SAME: float [[V:%.*]], ptr [[P:%.*]]) {
+; BE-MEMSSA-NEXT: store float [[V]], ptr [[P]], align 4
+; BE-MEMSSA-NEXT: [[A:%.*]] = load ptr, ptr [[P]], align 4
+; BE-MEMSSA-NEXT: ret ptr [[A]]
;
store float %V, ptr %P
@@ -96,14 +176,47 @@ define ptr @coerce_mustalias3(float %V, ptr %P) {
;; i32 -> f32 load forwarding.
define float @coerce_mustalias4(ptr %P, i1 %cond) {
-; CHECK-LABEL: @coerce_mustalias4(
-; CHECK-NEXT: [[A:%.*]] = load i32, ptr [[P:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[A]] to float
-; CHECK-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
-; CHECK: T:
-; CHECK-NEXT: ret float [[TMP1]]
-; CHECK: F:
-; CHECK-NEXT: ret float [[TMP1]]
+; LE-MEMDEP-LABEL: define float @coerce_mustalias4(
+; LE-MEMDEP-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; LE-MEMDEP-NEXT: [[A:%.*]] = load i32, ptr [[P]], align 4
+; LE-MEMDEP-NEXT: [[TMP1:%.*]] = bitcast i32 [[A]] to float
+; LE-MEMDEP-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; LE-MEMDEP: [[T]]:
+; LE-MEMDEP-NEXT: ret float [[TMP1]]
+; LE-MEMDEP: [[F]]:
+; LE-MEMDEP-NEXT: ret float [[TMP1]]
+;
+; LE-MEMSSA-LABEL: define float @coerce_mustalias4(
+; LE-MEMSSA-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; LE-MEMSSA-NEXT: [[A:%.*]] = load i32, ptr [[P]], align 4
+; LE-MEMSSA-NEXT: [[B:%.*]] = load float, ptr [[P]], align 4
+; LE-MEMSSA-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; LE-MEMSSA: [[T]]:
+; LE-MEMSSA-NEXT: ret float [[B]]
+; LE-MEMSSA: [[F]]:
+; LE-MEMSSA-NEXT: [[X:%.*]] = bitcast i32 [[A]] to float
+; LE-MEMSSA-NEXT: ret float [[X]]
+;
+; BE-MEMDEP-LABEL: define float @coerce_mustalias4(
+; BE-MEMDEP-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; BE-MEMDEP-NEXT: [[A:%.*]] = load i32, ptr [[P]], align 4
+; BE-MEMDEP-NEXT: [[TMP1:%.*]] = bitcast i32 [[A]] to float
+; BE-MEMDEP-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; BE-MEMDEP: [[T]]:
+; BE-MEMDEP-NEXT: ret float [[TMP1]]
+; BE-MEMDEP: [[F]]:
+; BE-MEMDEP-NEXT: ret float [[TMP1]]
+;
+; BE-MEMSSA-LABEL: define float @coerce_mustalias4(
+; BE-MEMSSA-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; BE-MEMSSA-NEXT: [[A:%.*]] = load i32, ptr [[P]], align 4
+; BE-MEMSSA-NEXT: [[B:%.*]] = load float, ptr [[P]], align 4
+; BE-MEMSSA-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; BE-MEMSSA: [[T]]:
+; BE-MEMSSA-NEXT: ret float [[B]]
+; BE-MEMSSA: [[F]]:
+; BE-MEMSSA-NEXT: [[X:%.*]] = bitcast i32 [[A]] to float
+; BE-MEMSSA-NEXT: ret float [[X]]
;
%A = load i32, ptr %P
@@ -120,16 +233,30 @@ F:
;; i32 -> i8 forwarding
define i8 @coerce_mustalias5(i32 %V, ptr %P) {
-; LE-LABEL: @coerce_mustalias5(
-; LE-NEXT: store i32 [[V:%.*]], ptr [[P:%.*]], align 4
-; LE-NEXT: [[TMP1:%.*]] = trunc i32 [[V]] to i8
-; LE-NEXT: ret i8 [[TMP1]]
+; LE-MEMDEP-LABEL: define i8 @coerce_mustalias5(
+; LE-MEMDEP-SAME: i32 [[V:%.*]], ptr [[P:%.*]]) {
+; LE-MEMDEP-NEXT: store i32 [[V]], ptr [[P]], align 4
+; LE-MEMDEP-NEXT: [[TMP1:%.*]] = trunc i32 [[V]] to i8
+; LE-MEMDEP-NEXT: ret i8 [[TMP1]]
+;
+; LE-MEMSSA-LABEL: define i8 @coerce_mustalias5(
+; LE-MEMSSA-SAME: i32 [[V:%.*]], ptr [[P:%.*]]) {
+; LE-MEMSSA-NEXT: store i32 [[V]], ptr [[P]], align 4
+; LE-MEMSSA-NEXT: [[A:%.*]] = load i8, ptr [[P]], align 1
+; LE-MEMSSA-NEXT: ret i8 [[A]]
+;
+; BE-MEMDEP-LABEL: define i8 @coerce_mustalias5(
+; BE-MEMDEP-SAME: i32 [[V:%.*]], ptr [[P:%.*]]) {
+; BE-MEMDEP-NEXT: store i32 [[V]], ptr [[P]], align 4
+; BE-MEMDEP-NEXT: [[TMP1:%.*]] = lshr i32 [[V]], 24
+; BE-MEMDEP-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
+; BE-MEMDEP-NEXT: ret i8 [[TMP2]]
;
-; BE-LABEL: @coerce_mustalias5(
-; BE-NEXT: store i32 [[V:%.*]], ptr [[P:%.*]], align 4
-; BE-NEXT: [[TMP1:%.*]] = lshr i32 [[V]], 24
-; BE-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
-; BE-NEXT: ret i8 [[TMP2]]
+; BE-MEMSSA-LABEL: define i8 @coerce_mustalias5(
+; BE-MEMSSA-SAME: i32 [[V:%.*]], ptr [[P:%.*]]) {
+; BE-MEMSSA-NEXT: store i32 [[V]], ptr [[P]], align 4
+; BE-MEMSSA-NEXT: [[A:%.*]] = load i8, ptr [[P]], align 1
+; BE-MEMSSA-NEXT: ret i8 [[A]]
;
store i32 %V, ptr %P
@@ -140,18 +267,32 @@ define i8 @coerce_mustalias5(i32 %V, ptr %P) {
;; i64 -> float forwarding
define float @coerce_mustalias6(i64 %V, ptr %P) {
-; LE-LABEL: @coerce_mustalias6(
-; LE-NEXT: store i64 [[V:%.*]], ptr [[P:%.*]], align 4
-; LE-NEXT: [[TMP1:%.*]] = trunc i64 [[V]] to i32
-; LE-NEXT: [[TMP2:%.*]] = bitcast i32 [[TMP1]] to float
-; LE-NEXT: ret float [[TMP2]]
-;
-; BE-LABEL: @coerce_mustalias6(
-; BE-NEXT: store i64 [[V:%.*]], ptr [[P:%.*]], align 4
-; BE-NEXT: [[TMP1:%.*]] = lshr i64 [[V]], 32
-; BE-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32
-; BE-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float
-; BE-NEXT: ret float [[TMP3]]
+; LE-MEMDEP-LABEL: define float @coerce_mustalias6(
+; LE-MEMDEP-SAME: i64 [[V:%.*]], ptr [[P:%.*]]) {
+; LE-MEMDEP-NEXT: store i64 [[V]], ptr [[P]], align 4
+; LE-MEMDEP-NEXT: [[TMP1:%.*]] = trunc i64 [[V]] to i32
+; LE-MEMDEP-NEXT: [[TMP2:%.*]] = bitcast i32 [[TMP1]] to float
+; LE-MEMDEP-NEXT: ret float [[TMP2]]
+;
+; LE-MEMSSA-LABEL: define float @coerce_mustalias6(
+; LE-MEMSSA-SAME: i64 [[V:%.*]], ptr [[P:%.*]]) {
+; LE-MEMSSA-NEXT: store i64 [[V]], ptr [[P]], align 4
+; LE-MEMSSA-NEXT: [[A:%.*]] = load float, ptr [[P]], align 4
+; LE-MEMSSA-NEXT: ret float [[A]]
+;
+; BE-MEMDEP-LABEL: define float @coerce_mustalias6(
+; BE-MEMDEP-SAME: i64 [[V:%.*]], ptr [[P:%.*]]) {
+; BE-MEMDEP-NEXT: store i64 [[V]], ptr [[P]], align 4
+; BE-MEMDEP-NEXT: [[TMP1:%.*]] = lshr i64 [[V]], 32
+; BE-MEMDEP-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32
+; BE-MEMDEP-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float
+; BE-MEMDEP-NEXT: ret float [[TMP3]]
+;
+; BE-MEMSSA-LABEL: define float @coerce_mustalias6(
+; BE-MEMSSA-SAME: i64 [[V:%.*]], ptr [[P:%.*]]) {
+; BE-MEMSSA-NEXT: store i64 [[V]], ptr [[P]], align 4
+; BE-MEMSSA-NEXT: [[A:%.*]] = load float, ptr [[P]], align 4
+; BE-MEMSSA-NEXT: ret float [[A]]
;
store i64 %V, ptr %P
@@ -162,18 +303,32 @@ define float @coerce_mustalias6(i64 %V, ptr %P) {
;; i64 -> ptr (32-bit) forwarding
define ptr @coerce_mustalias7(i64 %V, ptr %P) {
-; LE-LABEL: @coerce_mustalias7(
-; LE-NEXT: store i64 [[V:%.*]], ptr [[P:%.*]], align 4
-; LE-NEXT: [[TMP1:%.*]] = trunc i64 [[V]] to i32
-; LE-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr
-; LE-NEXT: ret ptr [[TMP2]]
-;
-; BE-LABEL: @coerce_mustalias7(
-; BE-NEXT: store i64 [[V:%.*]], ptr [[P:%.*]], align 4
-; BE-NEXT: [[TMP1:%.*]] = lshr i64 [[V]], 32
-; BE-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32
-; BE-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr
-; BE-NEXT: ret ptr [[TMP3]]
+; LE-MEMDEP-LABEL: define ptr @coerce_mustalias7(
+; LE-MEMDEP-SAME: i64 [[V:%.*]], ptr [[P:%.*]]) {
+; LE-MEMDEP-NEXT: store i64 [[V]], ptr [[P]], align 4
+; LE-MEMDEP-NEXT: [[TMP1:%.*]] = trunc i64 [[V]] to i32
+; LE-MEMDEP-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr
+; LE-MEMDEP-NEXT: ret ptr [[TMP2]]
+;
+; LE-MEMSSA-LABEL: define ptr @coerce_mustalias7(
+; LE-MEMSSA-SAME: i64 [[V:%.*]], ptr [[P:%.*]]) {
+; LE-MEMSSA-NEXT: store i64 [[V]], ptr [[P]], align 4
+; LE-MEMSSA-NEXT: [[A:%.*]] = load ptr, ptr [[P]], align 4
+; LE-MEMSSA-NEXT: ret ptr [[A]]
+;
+; BE-MEMDEP-LABEL: define ptr @coerce_mustalias7(
+; BE-MEMDEP-SAME: i64 [[V:%.*]], ptr [[P:%.*]]) {
+; BE-MEMDEP-NEXT: store i64 [[V]], ptr [[P]], align 4
+; BE-MEMDEP-NEXT: [[TMP1:%.*]] = lshr i64 [[V]], 32
+; BE-MEMDEP-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32
+; BE-MEMDEP-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr
+; BE-MEMDEP-NEXT: ret ptr [[TMP3]]
+;
+; BE-MEMSSA-LABEL: define ptr @coerce_mustalias7(
+; BE-MEMSSA-SAME: i64 [[V:%.*]], ptr [[P:%.*]]) {
+; BE-MEMSSA-NEXT: store i64 [[V]], ptr [[P]], align 4
+; BE-MEMSSA-NEXT: [[A:%.*]] = load ptr, ptr [[P]], align 4
+; BE-MEMSSA-NEXT: ret ptr [[A]]
;
store i64 %V, ptr %P
@@ -184,10 +339,33 @@ define ptr @coerce_mustalias7(i64 %V, ptr %P) {
; memset -> i16 forwarding.
define signext i16 @memset_to_i16_local(ptr %A) nounwind ssp {
-; CHECK-LABEL: @memset_to_i16_local(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: tail call void @llvm.memset.p0.i64(ptr [[A:%.*]], i8 1, i64 200, i1 false)
-; CHECK-NEXT: ret i16 257
+; LE-MEMDEP-LABEL: define signext i16 @memset_to_i16_local(
+; LE-MEMDEP-SAME: ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {
+; LE-MEMDEP-NEXT: [[ENTRY:.*:]]
+; LE-MEMDEP-NEXT: tail call void @llvm.memset.p0.i64(ptr [[A]], i8 1, i64 200, i1 false)
+; LE-MEMDEP-NEXT: ret i16 257
+;
+; LE-MEMSSA-LABEL: define signext i16 @memset_to_i16_local(
+; LE-MEMSSA-SAME: ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {
+; LE-MEMSSA-NEXT: [[ENTRY:.*:]]
+; LE-MEMSSA-NEXT: tail call void @llvm.memset.p0.i64(ptr [[A]], i8 1, i64 200, i1 false)
+; LE-MEMSSA-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[A]], i64 42
+; LE-MEMSSA-NEXT: [[TTMP2:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
+; LE-MEMSSA-NEXT: ret i16 [[TTMP2]]
+;
+; BE-MEMDEP-LABEL: define signext i16 @memset_to_i16_local(
+; BE-MEMDEP-SAME: ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {
+; BE-MEMDEP-NEXT: [[ENTRY:.*:]]
+; BE-MEMDEP-NEXT: tail call void @llvm.memset.p0.i64(ptr [[A]], i8 1, i64 200, i1 false)
+; BE-MEMDEP-NEXT: ret i16 257
+;
+; BE-MEMSSA-LABEL: define signext i16 @memset_to_i16_local(
+; BE-MEMSSA-SAME: ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {
+; BE-MEMSSA-NEXT: [[ENTRY:.*:]]
+; BE-MEMSSA-NEXT: tail call void @llvm.memset.p0.i64(ptr [[A]], i8 1, i64 200, i1 false)
+; BE-MEMSSA-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[A]], i64 42
+; BE-MEMSSA-NEXT: [[TTMP2:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
+; BE-MEMSSA-NEXT: ret i16 [[TTMP2]]
;
entry:
tail call void @llvm.memset.p0.i64(ptr %A, i8 1, i64 200, i1 false)
@@ -198,16 +376,45 @@ entry:
; memset -> float forwarding.
define float @memset_to_float_local(ptr %A, i8 %Val) nounwind ssp {
-; CHECK-LABEL: @memset_to_float_local(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: tail call void @llvm.memset.p0.i64(ptr [[A:%.*]], i8 [[VAL:%.*]], i64 400, i1 false)
-; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[VAL]] to i32
-; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[TMP0]], 8
-; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP0]], [[TMP1]]
-; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[TMP2]], 16
-; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float
-; CHECK-NEXT: ret float [[TMP5]]
+; LE-MEMDEP-LABEL: define float @memset_to_float_local(
+; LE-MEMDEP-SAME: ptr [[A:%.*]], i8 [[VAL:%.*]]) #[[ATTR0]] {
+; LE-MEMDEP-NEXT: [[ENTRY:.*:]]
+; LE-MEMDEP-NEXT: tail call void @llvm.memset.p0.i64(ptr [[A]], i8 [[VAL]], i64 400, i1 false)
+; LE-MEMDEP-NEXT: [[TMP0:%.*]] = zext i8 [[VAL]] to i32
+; LE-MEMDEP-NEXT: [[TMP1:%.*]] = shl i32 [[TMP0]], 8
+; LE-MEMDEP-NEXT: [[TMP2:%.*]] = or i32 [[TMP0]], [[TMP1]]
+; LE-MEMDEP-NEXT: [[TMP3:%.*]] = shl i32 [[TMP2]], 16
+; LE-MEMDEP-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
+; LE-MEMDEP-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float
+; LE-MEMDEP-NEXT: ret float [[TMP5]]
+;
+; LE-MEMSSA-LABEL: define float @memset_to_float_local(
+; LE-MEMSSA-SAME: ptr [[A:%.*]], i8 [[VAL:%.*]]) #[[ATTR0]] {
+; LE-MEMSSA-NEXT: [[ENTRY:.*:]]
+; LE-MEMSSA-NEXT: tail call void @llvm.memset.p0.i64(ptr [[A]], i8 [[VAL]], i64 400, i1 false)
+; LE-MEMSSA-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 42
+; LE-MEMSSA-NEXT: [[TTMP2:%.*]] = load float, ptr [[ARRAYIDX]], align 4
+; LE-MEMSSA-NEXT: ret float [[TTMP2]]
+;
+; BE-MEMDEP-LABEL: define float @memset_to_float_local(
+; BE-MEMDEP-SAME: ptr [[A:%.*]], i8 [[VAL:%.*]]) #[[ATTR0]] {
+; BE-MEMDEP-NEXT: [[ENTRY:.*:]]
+; BE-MEMDEP-NEXT: tail call void @llvm.memset.p0.i64(ptr [[A]], i8 [[VAL]], i64 400, i1 false)
+; BE-MEMDEP-NEXT: [[TMP0:%.*]] = zext i8 [[VAL]] to i32
+; BE-MEMDEP-NEXT: [[TMP1:%.*]] = shl i32 [[TMP0]], 8
+; BE-MEMDEP-NEXT: [[TMP2:%.*]] = or i32 [[TMP0]], [[TMP1]]
+; BE-MEMDEP-NEXT: [[TMP3:%.*]] = shl i32 [[TMP2]], 16
+; BE-MEMDEP-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
+; BE-MEMDEP-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float
+; BE-MEMDEP-NEXT: ret float [[TMP5]]
+;
+; BE-MEMSSA-LABEL: define float @memset_to_float_local(
+; BE-MEMSSA-SAME: ptr [[A:%.*]], i8 [[VAL:%.*]]) #[[ATTR0]] {
+; BE-MEMSSA-NEXT: [[ENTRY:.*:]]
+; BE-MEMSSA-NEXT: tail call void @llvm.memset.p0.i64(ptr [[A]], i8 [[VAL]], i64 400, i1 false)
+; BE-MEMSSA-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 42
+; BE-MEMSSA-NEXT: [[TTMP2:%.*]] = load float, ptr [[ARRAYIDX]], align 4
+; BE-MEMSSA-NEXT: ret float [[TTMP2]]
;
entry:
tail call void @llvm.memset.p0.i64(ptr %A, i8 %Val, i64 400, i1 false)
@@ -218,17 +425,59 @@ entry:
;; non-local memset -> i16 load forwarding.
define i16 @memset_to_i16_nonlocal0(ptr %P, i1 %cond) {
-; CHECK-LABEL: @memset_to_i16_nonlocal0(
-; CHECK-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
-; CHECK: T:
-; CHECK-NEXT: tail call void @llvm.memset.p0.i64(ptr [[P:%.*]], i8 1, i64 400, i1 false)
-; CHECK-NEXT: br label [[CONT:%.*]]
-; CHECK: F:
-; CHECK-NEXT: tail call void @llvm.memset.p0.i64(ptr [[P]], i8 2, i64 400, i1 false)
-; CHECK-NEXT: br label [[CONT]]
-; CHECK: Cont:
-; CHECK-NEXT: [[A:%.*]] = phi i16 [ 514, [[F]] ], [ 257, [[T]] ]
-; CHECK-NEXT: ret i16 [[A]]
+; LE-MEMDEP-LABEL: define i16 @memset_to_i16_nonlocal0(
+; LE-MEMDEP-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; LE-MEMDEP-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; LE-MEMDEP: [[T]]:
+; LE-MEMDEP-NEXT: tail call void @llvm.memset.p0.i64(ptr [[P]], i8 1, i64 400, i1 false)
+; LE-MEMDEP-NEXT: br label %[[CONT:.*]]
+; LE-MEMDEP: [[F]]:
+; LE-MEMDEP-NEXT: tail call void @llvm.memset.p0.i64(ptr [[P]], i8 2, i64 400, i1 false)
+; LE-MEMDEP-NEXT: br label %[[CONT]]
+; LE-MEMDEP: [[CONT]]:
+; LE-MEMDEP-NEXT: [[A:%.*]] = phi i16 [ 514, %[[F]] ], [ 257, %[[T]] ]
+; LE-MEMDEP-NEXT: ret i16 [[A]]
+;
+; LE-MEMSSA-LABEL: define i16 @memset_to_i16_nonlocal0(
+; LE-MEMSSA-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; LE-MEMSSA-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; LE-MEMSSA: [[T]]:
+; LE-MEMSSA-NEXT: tail call void @llvm.memset.p0.i64(ptr [[P]], i8 1, i64 400, i1 false)
+; LE-MEMSSA-NEXT: br label %[[CONT:.*]]
+; LE-MEMSSA: [[F]]:
+; LE-MEMSSA-NEXT: tail call void @llvm.memset.p0.i64(ptr [[P]], i8 2, i64 400, i1 false)
+; LE-MEMSSA-NEXT: br label %[[CONT]]
+; LE-MEMSSA: [[CONT]]:
+; LE-MEMSSA-NEXT: [[P2:%.*]] = getelementptr i16, ptr [[P]], i32 4
+; LE-MEMSSA-NEXT: [[A:%.*]] = load i16, ptr [[P2]], align 2
+; LE-MEMSSA-NEXT: ret i16 [[A]]
+;
+; BE-MEMDEP-LABEL: define i16 @memset_to_i16_nonlocal0(
+; BE-MEMDEP-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; BE-MEMDEP-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; BE-MEMDEP: [[T]]:
+; BE-MEMDEP-NEXT: tail call void @llvm.memset.p0.i64(ptr [[P]], i8 1, i64 400, i1 false)
+; BE-MEMDEP-NEXT: br label %[[CONT:.*]]
+; BE-MEMDEP: [[F]]:
+; BE-MEMDEP-NEXT: tail call void @llvm.memset.p0.i64(ptr [[P]], i8 2, i64 400, i1 false)
+; BE-MEMDEP-NEXT: br label %[[CONT]]
+; BE-MEMDEP: [[CONT]]:
+; BE-MEMDEP-NEXT: [[A:%.*]] = phi i16 [ 514, %[[F]] ], [ 257, %[[T]] ]
+; BE-MEMDEP-NEXT: ret i16 [[A]]
+;
+; BE-MEMSSA-LABEL: define i16 @memset_to_i16_nonlocal0(
+; BE-MEMSSA-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; BE-MEMSSA-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; BE-MEMSSA: [[T]]:
+; BE-MEMSSA-NEXT: tail call void @llvm.memset.p0.i64(ptr [[P]], i8 1, i64 400, i1 false)
+; BE-MEMSSA-NEXT: br label %[[CONT:.*]]
+; BE-MEMSSA: [[F]]:
+; BE-MEMSSA-NEXT: tail call void @llvm.memset.p0.i64(ptr [[P]], i8 2, i64 400, i1 false)
+; BE-MEMSSA-NEXT: br label %[[CONT]]
+; BE-MEMSSA: [[CONT]]:
+; BE-MEMSSA-NEXT: [[P2:%.*]] = getelementptr i16, ptr [[P]], i32 4
+; BE-MEMSSA-NEXT: [[A:%.*]] = load i16, ptr [[P2]], align 2
+; BE-MEMSSA-NEXT: ret i16 [[A]]
;
br i1 %cond, label %T, label %F
T:
@@ -251,10 +500,33 @@ Cont:
; memset -> float forwarding.
define float @memcpy_to_float_local(ptr %A) nounwind ssp {
-; CHECK-LABEL: @memcpy_to_float_local(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: tail call void @llvm.memcpy.p0.p0.i64(ptr [[A:%.*]], ptr @GCst, i64 12, i1 false)
-; CHECK-NEXT: ret float 1.400000e+01
+; LE-MEMDEP-LABEL: define float @memcpy_to_float_local(
+; LE-MEMDEP-SAME: ptr [[A:%.*]]) #[[ATTR0]] {
+; LE-MEMDEP-NEXT: [[ENTRY:.*:]]
+; LE-MEMDEP-NEXT: tail call void @llvm.memcpy.p0.p0.i64(ptr [[A]], ptr @GCst, i64 12, i1 false)
+; LE-MEMDEP-NEXT: ret float 1.400000e+01
+;
+; LE-MEMSSA-LABEL: define float @memcpy_to_float_local(
+; LE-MEMSSA-SAME: ptr [[A:%.*]]) #[[ATTR0]] {
+; LE-MEMSSA-NEXT: [[ENTRY:.*:]]
+; LE-MEMSSA-NEXT: tail call void @llvm.memcpy.p0.p0.i64(ptr [[A]], ptr @GCst, i64 12, i1 false)
+; LE-MEMSSA-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 1
+; LE-MEMSSA-NEXT: [[TTMP2:%.*]] = load float, ptr [[ARRAYIDX]], align 4
+; LE-MEMSSA-NEXT: ret float [[TTMP2]]
+;
+; BE-MEMDEP-LABEL: define float @memcpy_to_float_local(
+; BE-MEMDEP-SAME: ptr [[A:%.*]]) #[[ATTR0]] {
+; BE-MEMDEP-NEXT: [[ENTRY:.*:]]
+; BE-MEMDEP-NEXT: tail call void @llvm.memcpy.p0.p0.i64(ptr [[A]], ptr @GCst, i64 12, i1 false)
+; BE-MEMDEP-NEXT: ret float 1.400000e+01
+;
+; BE-MEMSSA-LABEL: define float @memcpy_to_float_local(
+; BE-MEMSSA-SAME: ptr [[A:%.*]]) #[[ATTR0]] {
+; BE-MEMSSA-NEXT: [[ENTRY:.*:]]
+; BE-MEMSSA-NEXT: tail call void @llvm.memcpy.p0.p0.i64(ptr [[A]], ptr @GCst, i64 12, i1 false)
+; BE-MEMSSA-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 1
+; BE-MEMSSA-NEXT: [[TTMP2:%.*]] = load float, ptr [[ARRAYIDX]], align 4
+; BE-MEMSSA-NEXT: ret float [[TTMP2]]
;
entry:
tail call void @llvm.memcpy.p0.p0.i64(ptr %A, ptr @GCst, i64 12, i1 false)
@@ -265,10 +537,33 @@ entry:
; memcpy from address space 1
define float @memcpy_to_float_local_as1(ptr %A) nounwind ssp {
-; CHECK-LABEL: @memcpy_to_float_local_as1(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: tail call void @llvm.memcpy.p0.p1.i64(ptr [[A:%.*]], ptr addrspace(1) @GCst_as1, i64 12, i1 false)
-; CHECK-NEXT: ret float 1.400000e+01
+; LE-MEMDEP-LABEL: define float @memcpy_to_float_local_as1(
+; LE-MEMDEP-SAME: ptr [[A:%.*]]) #[[ATTR0]] {
+; LE-MEMDEP-NEXT: [[ENTRY:.*:]]
+; LE-MEMDEP-NEXT: tail call void @llvm.memcpy.p0.p1.i64(ptr [[A]], ptr addrspace(1) @GCst_as1, i64 12, i1 false)
+; LE-MEMDEP-NEXT: ret float 1.400000e+01
+;
+; LE-MEMSSA-LABEL: define float @memcpy_to_float_local_as1(
+; LE-MEMSSA-SAME: ptr [[A:%.*]]) #[[ATTR0]] {
+; LE-MEMSSA-NEXT: [[ENTRY:.*:]]
+; LE-MEMSSA-NEXT: tail call void @llvm.memcpy.p0.p1.i64(ptr [[A]], ptr addrspace(1) @GCst_as1, i64 12, i1 false)
+; LE-MEMSSA-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 1
+; LE-MEMSSA-NEXT: [[TTMP2:%.*]] = load float, ptr [[ARRAYIDX]], align 4
+; LE-MEMSSA-NEXT: ret float [[TTMP2]]
+;
+; BE-MEMDEP-LABEL: define float @memcpy_to_float_local_as1(
+; BE-MEMDEP-SAME: ptr [[A:%.*]]) #[[ATTR0]] {
+; BE-MEMDEP-NEXT: [[ENTRY:.*:]]
+; BE-MEMDEP-NEXT: tail call void @llvm.memcpy.p0.p1.i64(ptr [[A]], ptr addrspace(1) @GCst_as1, i64 12, i1 false)
+; BE-MEMDEP-NEXT: ret float 1.400000e+01
+;
+; BE-MEMSSA-LABEL: define float @memcpy_to_float_local_as1(
+; BE-MEMSSA-SAME: ptr [[A:%.*]]) #[[ATTR0]] {
+; BE-MEMSSA-NEXT: [[ENTRY:.*:]]
+; BE-MEMSSA-NEXT: tail call void @llvm.memcpy.p0.p1.i64(ptr [[A]], ptr addrspace(1) @GCst_as1, i64 12, i1 false)
+; BE-MEMSSA-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 1
+; BE-MEMSSA-NEXT: [[TTMP2:%.*]] = load float, ptr [[ARRAYIDX]], align 4
+; BE-MEMSSA-NEXT: ret float [[TTMP2]]
;
entry:
tail call void @llvm.memcpy.p0.p1.i64(ptr %A, ptr addrspace(1) @GCst_as1, i64 12, i1 false)
@@ -279,29 +574,57 @@ entry:
;; non-local i32/float -> i8 load forwarding.
define i8 @coerce_mustalias_nonlocal0(ptr %P, i1 %cond) {
-; LE-LABEL: @coerce_mustalias_nonlocal0(
-; LE-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
-; LE: T:
-; LE-NEXT: store i32 42, ptr [[P:%.*]], align 4
-; LE-NEXT: br label [[CONT:%.*]]
-; LE: F:
-; LE-NEXT: store float 1.000000e+00, ptr [[P]], align 4
-; LE-NEXT: br label [[CONT]]
-; LE: Cont:
-; LE-NEXT: [[A:%.*]] = phi i8 [ 0, [[F]] ], [ 42, [[T]] ]
-; LE-NEXT: ret i8 [[A]]
-;
-; BE-LABEL: @coerce_mustalias_nonlocal0(
-; BE-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
-; BE: T:
-; BE-NEXT: store i32 42, ptr [[P:%.*]], align 4
-; BE-NEXT: br label [[CONT:%.*]]
-; BE: F:
-; BE-NEXT: store float 1.000000e+00, ptr [[P]], align 4
-; BE-NEXT: br label [[CONT]]
-; BE: Cont:
-; BE-NEXT: [[A:%.*]] = phi i8 [ 63, [[F]] ], [ 0, [[T]] ]
-; BE-NEXT: ret i8 [[A]]
+; LE-MEMDEP-LABEL: define i8 @coerce_mustalias_nonlocal0(
+; LE-MEMDEP-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; LE-MEMDEP-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; LE-MEMDEP: [[T]]:
+; LE-MEMDEP-NEXT: store i32 42, ptr [[P]], align 4
+; LE-MEMDEP-NEXT: br label %[[CONT:.*]]
+; LE-MEMDEP: [[F]]:
+; LE-MEMDEP-NEXT: store float 1.000000e+00, ptr [[P]], align 4
+; LE-MEMDEP-NEXT: br label %[[CONT]]
+; LE-MEMDEP: [[CONT]]:
+; LE-MEMDEP-NEXT: [[A:%.*]] = phi i8 [ 0, %[[F]] ], [ 42, %[[T]] ]
+; LE-MEMDEP-NEXT: ret i8 [[A]]
+;
+; LE-MEMSSA-LABEL: define i8 @coerce_mustalias_nonlocal0(
+; LE-MEMSSA-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; LE-MEMSSA-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; LE-MEMSSA: [[T]]:
+; LE-MEMSSA-NEXT: store i32 42, ptr [[P]], align 4
+; LE-MEMSSA-NEXT: br label %[[CONT:.*]]
+; LE-MEMSSA: [[F]]:
+; LE-MEMSSA-NEXT: store float 1.000000e+00, ptr [[P]], align 4
+; LE-MEMSSA-NEXT: br label %[[CONT]]
+; LE-MEMSSA: [[CONT]]:
+; LE-MEMSSA-NEXT: [[A:%.*]] = load i8, ptr [[P]], align 1
+; LE-MEMSSA-NEXT: ret i8 [[A]]
+;
+; BE-MEMDEP-LABEL: define i8 @coerce_mustalias_nonlocal0(
+; BE-MEMDEP-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; BE-MEMDEP-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; BE-MEMDEP: [[T]]:
+; BE-MEMDEP-NEXT: store i32 42, ptr [[P]], align 4
+; BE-MEMDEP-NEXT: br label %[[CONT:.*]]
+; BE-MEMDEP: [[F]]:
+; BE-MEMDEP-NEXT: store float 1.000000e+00, ptr [[P]], align 4
+; BE-MEMDEP-NEXT: br label %[[CONT]]
+; BE-MEMDEP: [[CONT]]:
+; BE-MEMDEP-NEXT: [[A:%.*]] = phi i8 [ 63, %[[F]] ], [ 0, %[[T]] ]
+; BE-MEMDEP-NEXT: ret i8 [[A]]
+;
+; BE-MEMSSA-LABEL: define i8 @coerce_mustalias_nonlocal0(
+; BE-MEMSSA-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; BE-MEMSSA-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; BE-MEMSSA: [[T]]:
+; BE-MEMSSA-NEXT: store i32 42, ptr [[P]], align 4
+; BE-MEMSSA-NEXT: br label %[[CONT:.*]]
+; BE-MEMSSA: [[F]]:
+; BE-MEMSSA-NEXT: store float 1.000000e+00, ptr [[P]], align 4
+; BE-MEMSSA-NEXT: br label %[[CONT]]
+; BE-MEMSSA: [[CONT]]:
+; BE-MEMSSA-NEXT: [[A:%.*]] = load i8, ptr [[P]], align 1
+; BE-MEMSSA-NEXT: ret i8 [[A]]
;
br i1 %cond, label %T, label %F
T:
@@ -322,29 +645,57 @@ Cont:
;; non-local i32/float -> i8 load forwarding. This also tests that the "P3"
;; bitcast equivalence can be properly phi translated.
define i8 @coerce_mustalias_nonlocal1(ptr %P, i1 %cond) {
-; LE-LABEL: @coerce_mustalias_nonlocal1(
-; LE-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
-; LE: T:
-; LE-NEXT: store i32 42, ptr [[P:%.*]], align 4
-; LE-NEXT: br label [[CONT:%.*]]
-; LE: F:
-; LE-NEXT: store float 1.000000e+00, ptr [[P]], align 4
-; LE-NEXT: br label [[CONT]]
-; LE: Cont:
-; LE-NEXT: [[A:%.*]] = phi i8 [ 0, [[F]] ], [ 42, [[T]] ]
-; LE-NEXT: ret i8 [[A]]
-;
-; BE-LABEL: @coerce_mustalias_nonlocal1(
-; BE-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
-; BE: T:
-; BE-NEXT: store i32 42, ptr [[P:%.*]], align 4
-; BE-NEXT: br label [[CONT:%.*]]
-; BE: F:
-; BE-NEXT: store float 1.000000e+00, ptr [[P]], align 4
-; BE-NEXT: br label [[CONT]]
-; BE: Cont:
-; BE-NEXT: [[A:%.*]] = phi i8 [ 63, [[F]] ], [ 0, [[T]] ]
-; BE-NEXT: ret i8 [[A]]
+; LE-MEMDEP-LABEL: define i8 @coerce_mustalias_nonlocal1(
+; LE-MEMDEP-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; LE-MEMDEP-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; LE-MEMDEP: [[T]]:
+; LE-MEMDEP-NEXT: store i32 42, ptr [[P]], align 4
+; LE-MEMDEP-NEXT: br label %[[CONT:.*]]
+; LE-MEMDEP: [[F]]:
+; LE-MEMDEP-NEXT: store float 1.000000e+00, ptr [[P]], align 4
+; LE-MEMDEP-NEXT: br label %[[CONT]]
+; LE-MEMDEP: [[CONT]]:
+; LE-MEMDEP-NEXT: [[A:%.*]] = phi i8 [ 0, %[[F]] ], [ 42, %[[T]] ]
+; LE-MEMDEP-NEXT: ret i8 [[A]]
+;
+; LE-MEMSSA-LABEL: define i8 @coerce_mustalias_nonlocal1(
+; LE-MEMSSA-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; LE-MEMSSA-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; LE-MEMSSA: [[T]]:
+; LE-MEMSSA-NEXT: store i32 42, ptr [[P]], align 4
+; LE-MEMSSA-NEXT: br label %[[CONT:.*]]
+; LE-MEMSSA: [[F]]:
+; LE-MEMSSA-NEXT: store float 1.000000e+00, ptr [[P]], align 4
+; LE-MEMSSA-NEXT: br label %[[CONT]]
+; LE-MEMSSA: [[CONT]]:
+; LE-MEMSSA-NEXT: [[A:%.*]] = load i8, ptr [[P]], align 1
+; LE-MEMSSA-NEXT: ret i8 [[A]]
+;
+; BE-MEMDEP-LABEL: define i8 @coerce_mustalias_nonlocal1(
+; BE-MEMDEP-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; BE-MEMDEP-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; BE-MEMDEP: [[T]]:
+; BE-MEMDEP-NEXT: store i32 42, ptr [[P]], align 4
+; BE-MEMDEP-NEXT: br label %[[CONT:.*]]
+; BE-MEMDEP: [[F]]:
+; BE-MEMDEP-NEXT: store float 1.000000e+00, ptr [[P]], align 4
+; BE-MEMDEP-NEXT: br label %[[CONT]]
+; BE-MEMDEP: [[CONT]]:
+; BE-MEMDEP-NEXT: [[A:%.*]] = phi i8 [ 63, %[[F]] ], [ 0, %[[T]] ]
+; BE-MEMDEP-NEXT: ret i8 [[A]]
+;
+; BE-MEMSSA-LABEL: define i8 @coerce_mustalias_nonlocal1(
+; BE-MEMSSA-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; BE-MEMSSA-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; BE-MEMSSA: [[T]]:
+; BE-MEMSSA-NEXT: store i32 42, ptr [[P]], align 4
+; BE-MEMSSA-NEXT: br label %[[CONT:.*]]
+; BE-MEMSSA: [[F]]:
+; BE-MEMSSA-NEXT: store float 1.000000e+00, ptr [[P]], align 4
+; BE-MEMSSA-NEXT: br label %[[CONT]]
+; BE-MEMSSA: [[CONT]]:
+; BE-MEMSSA-NEXT: [[A:%.*]] = load i8, ptr [[P]], align 1
+; BE-MEMSSA-NEXT: ret i8 [[A]]
;
br i1 %cond, label %T, label %F
T:
@@ -364,29 +715,55 @@ Cont:
;; non-local i32 -> i8 partial redundancy load forwarding.
define i8 @coerce_mustalias_pre0(ptr %P, i1 %cond) {
-; LE-LABEL: @coerce_mustalias_pre0(
-; LE-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
-; LE: T:
-; LE-NEXT: store i32 42, ptr [[P:%.*]], align 4
-; LE-NEXT: br label [[CONT:%.*]]
-; LE: F:
-; LE-NEXT: [[A_PRE:%.*]] = load i8, ptr [[P]], align 1
-; LE-NEXT: br label [[CONT]]
-; LE: Cont:
-; LE-NEXT: [[A:%.*]] = phi i8 [ [[A_PRE]], [[F]] ], [ 42, [[T]] ]
-; LE-NEXT: ret i8 [[A]]
-;
-; BE-LABEL: @coerce_mustalias_pre0(
-; BE-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
-; BE: T:
-; BE-NEXT: store i32 42, ptr [[P:%.*]], align 4
-; BE-NEXT: br label [[CONT:%.*]]
-; BE: F:
-; BE-NEXT: [[A_PRE:%.*]] = load i8, ptr [[P]], align 1
-; BE-NEXT: br label [[CONT]]
-; BE: Cont:
-; BE-NEXT: [[A:%.*]] = phi i8 [ [[A_PRE]], [[F]] ], [ 0, [[T]] ]
-; BE-NEXT: ret i8 [[A]]
+; LE-MEMDEP-LABEL: define i8 @coerce_mustalias_pre0(
+; LE-MEMDEP-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; LE-MEMDEP-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; LE-MEMDEP: [[T]]:
+; LE-MEMDEP-NEXT: store i32 42, ptr [[P]], align 4
+; LE-MEMDEP-NEXT: br label %[[CONT:.*]]
+; LE-MEMDEP: [[F]]:
+; LE-MEMDEP-NEXT: [[A_PRE:%.*]] = load i8, ptr [[P]], align 1
+; LE-MEMDEP-NEXT: br label %[[CONT]]
+; LE-MEMDEP: [[CONT]]:
+; LE-MEMDEP-NEXT: [[A:%.*]] = phi i8 [ [[A_PRE]], %[[F]] ], [ 42, %[[T]] ]
+; LE-MEMDEP-NEXT: ret i8 [[A]]
+;
+; LE-MEMSSA-LABEL: define i8 @coerce_mustalias_pre0(
+; LE-MEMSSA-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; LE-MEMSSA-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; LE-MEMSSA: [[T]]:
+; LE-MEMSSA-NEXT: store i32 42, ptr [[P]], align 4
+; LE-MEMSSA-NEXT: br label %[[CONT:.*]]
+; LE-MEMSSA: [[F]]:
+; LE-MEMSSA-NEXT: br label %[[CONT]]
+; LE-MEMSSA: [[CONT]]:
+; LE-MEMSSA-NEXT: [[A:%.*]] = load i8, ptr [[P]], align 1
+; LE-MEMSSA-NEXT: ret i8 [[A]]
+;
+; BE-MEMDEP-LABEL: define i8 @coerce_mustalias_pre0(
+; BE-MEMDEP-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; BE-MEMDEP-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; BE-MEMDEP: [[T]]:
+; BE-MEMDEP-NEXT: store i32 42, ptr [[P]], align 4
+; BE-MEMDEP-NEXT: br label %[[CONT:.*]]
+; BE-MEMDEP: [[F]]:
+; BE-MEMDEP-NEXT: [[A_PRE:%.*]] = load i8, ptr [[P]], align 1
+; BE-MEMDEP-NEXT: br label %[[CONT]]
+; BE-MEMDEP: [[CONT]]:
+; BE-MEMDEP-NEXT: [[A:%.*]] = phi i8 [ [[A_PRE]], %[[F]] ], [ 0, %[[T]] ]
+; BE-MEMDEP-NEXT: ret i8 [[A]]
+;
+; BE-MEMSSA-LABEL: define i8 @coerce_mustalias_pre0(
+; BE-MEMSSA-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; BE-MEMSSA-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; BE-MEMSSA: [[T]]:
+; BE-MEMSSA-NEXT: store i32 42, ptr [[P]], align 4
+; BE-MEMSSA-NEXT: br label %[[CONT:.*]]
+; BE-MEMSSA: [[F]]:
+; BE-MEMSSA-NEXT: br label %[[CONT]]
+; BE-MEMSSA: [[CONT]]:
+; BE-MEMSSA-NEXT: [[A:%.*]] = load i8, ptr [[P]], align 1
+; BE-MEMSSA-NEXT: ret i8 [[A]]
;
br i1 %cond, label %T, label %F
T:
@@ -410,17 +787,33 @@ Cont:
;; i32 -> i8 forwarding.
;; PR4216
define i8 @coerce_offset0(i32 %V, ptr %P) {
-; LE-LABEL: @coerce_offset0(
-; LE-NEXT: store i32 [[V:%.*]], ptr [[P:%.*]], align 4
-; LE-NEXT: [[TMP1:%.*]] = lshr i32 [[V]], 16
-; LE-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
-; LE-NEXT: ret i8 [[TMP2]]
-;
-; BE-LABEL: @coerce_offset0(
-; BE-NEXT: store i32 [[V:%.*]], ptr [[P:%.*]], align 4
-; BE-NEXT: [[TMP1:%.*]] = lshr i32 [[V]], 8
-; BE-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
-; BE-NEXT: ret i8 [[TMP2]]
+; LE-MEMDEP-LABEL: define i8 @coerce_offset0(
+; LE-MEMDEP-SAME: i32 [[V:%.*]], ptr [[P:%.*]]) {
+; LE-MEMDEP-NEXT: store i32 [[V]], ptr [[P]], align 4
+; LE-MEMDEP-NEXT: [[TMP1:%.*]] = lshr i32 [[V]], 16
+; LE-MEMDEP-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
+; LE-MEMDEP-NEXT: ret i8 [[TMP2]]
+;
+; LE-MEMSSA-LABEL: define i8 @coerce_offset0(
+; LE-MEMSSA-SAME: i32 [[V:%.*]], ptr [[P:%.*]]) {
+; LE-MEMSSA-NEXT: store i32 [[V]], ptr [[P]], align 4
+; LE-MEMSSA-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; LE-MEMSSA-NEXT: [[A:%.*]] = load i8, ptr [[P3]], align 1
+; LE-MEMSSA-NEXT: ret i8 [[A]]
+;
+; BE-MEMDEP-LABEL: define i8 @coerce_offset0(
+; BE-MEMDEP-SAME: i32 [[V:%.*]], ptr [[P:%.*]]) {
+; BE-MEMDEP-NEXT: store i32 [[V]], ptr [[P]], align 4
+; BE-MEMDEP-NEXT: [[TMP1:%.*]] = lshr i32 [[V]], 8
+; BE-MEMDEP-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
+; BE-MEMDEP-NEXT: ret i8 [[TMP2]]
+;
+; BE-MEMSSA-LABEL: define i8 @coerce_offset0(
+; BE-MEMSSA-SAME: i32 [[V:%.*]], ptr [[P:%.*]]) {
+; BE-MEMSSA-NEXT: store i32 [[V]], ptr [[P]], align 4
+; BE-MEMSSA-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; BE-MEMSSA-NEXT: [[A:%.*]] = load i8, ptr [[P3]], align 1
+; BE-MEMSSA-NEXT: ret i8 [[A]]
;
store i32 %V, ptr %P
@@ -432,29 +825,59 @@ define i8 @coerce_offset0(i32 %V, ptr %P) {
;; non-local i32/float -> i8 load forwarding.
define i8 @coerce_offset_nonlocal0(ptr %P, i1 %cond) {
-; LE-LABEL: @coerce_offset_nonlocal0(
-; LE-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
-; LE: T:
-; LE-NEXT: store i32 57005, ptr [[P:%.*]], align 4
-; LE-NEXT: br label [[CONT:%.*]]
-; LE: F:
-; LE-NEXT: store float 1.000000e+00, ptr [[P]], align 4
-; LE-NEXT: br label [[CONT]]
-; LE: Cont:
-; LE-NEXT: [[A:%.*]] = phi i8 [ -128, [[F]] ], [ 0, [[T]] ]
-; LE-NEXT: ret i8 [[A]]
-;
-; BE-LABEL: @coerce_offset_nonlocal0(
-; BE-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
-; BE: T:
-; BE-NEXT: store i32 57005, ptr [[P:%.*]], align 4
-; BE-NEXT: br label [[CONT:%.*]]
-; BE: F:
-; BE-NEXT: store float 1.000000e+00, ptr [[P]], align 4
-; BE-NEXT: br label [[CONT]]
-; BE: Cont:
-; BE-NEXT: [[A:%.*]] = phi i8 [ 0, [[F]] ], [ -34, [[T]] ]
-; BE-NEXT: ret i8 [[A]]
+; LE-MEMDEP-LABEL: define i8 @coerce_offset_nonlocal0(
+; LE-MEMDEP-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; LE-MEMDEP-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; LE-MEMDEP: [[T]]:
+; LE-MEMDEP-NEXT: store i32 57005, ptr [[P]], align 4
+; LE-MEMDEP-NEXT: br label %[[CONT:.*]]
+; LE-MEMDEP: [[F]]:
+; LE-MEMDEP-NEXT: store float 1.000000e+00, ptr [[P]], align 4
+; LE-MEMDEP-NEXT: br label %[[CONT]]
+; LE-MEMDEP: [[CONT]]:
+; LE-MEMDEP-NEXT: [[A:%.*]] = phi i8 [ -128, %[[F]] ], [ 0, %[[T]] ]
+; LE-MEMDEP-NEXT: ret i8 [[A]]
+;
+; LE-MEMSSA-LABEL: define i8 @coerce_offset_nonlocal0(
+; LE-MEMSSA-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; LE-MEMSSA-NEXT: [[P4:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; LE-MEMSSA-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; LE-MEMSSA: [[T]]:
+; LE-MEMSSA-NEXT: store i32 57005, ptr [[P]], align 4
+; LE-MEMSSA-NEXT: br label %[[CONT:.*]]
+; LE-MEMSSA: [[F]]:
+; LE-MEMSSA-NEXT: store float 1.000000e+00, ptr [[P]], align 4
+; LE-MEMSSA-NEXT: br label %[[CONT]]
+; LE-MEMSSA: [[CONT]]:
+; LE-MEMSSA-NEXT: [[A:%.*]] = load i8, ptr [[P4]], align 1
+; LE-MEMSSA-NEXT: ret i8 [[A]]
+;
+; BE-MEMDEP-LABEL: define i8 @coerce_offset_nonlocal0(
+; BE-MEMDEP-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; BE-MEMDEP-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; BE-MEMDEP: [[T]]:
+; BE-MEMDEP-NEXT: store i32 57005, ptr [[P]], align 4
+; BE-MEMDEP-NEXT: br label %[[CONT:.*]]
+; BE-MEMDEP: [[F]]:
+; BE-MEMDEP-NEXT: store float 1.000000e+00, ptr [[P]], align 4
+; BE-MEMDEP-NEXT: br label %[[CONT]]
+; BE-MEMDEP: [[CONT]]:
+; BE-MEMDEP-NEXT: [[A:%.*]] = phi i8 [ 0, %[[F]] ], [ -34, %[[T]] ]
+; BE-MEMDEP-NEXT: ret i8 [[A]]
+;
+; BE-MEMSSA-LABEL: define i8 @coerce_offset_nonlocal0(
+; BE-MEMSSA-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; BE-MEMSSA-NEXT: [[P4:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; BE-MEMSSA-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; BE-MEMSSA: [[T]]:
+; BE-MEMSSA-NEXT: store i32 57005, ptr [[P]], align 4
+; BE-MEMSSA-NEXT: br label %[[CONT:.*]]
+; BE-MEMSSA: [[F]]:
+; BE-MEMSSA-NEXT: store float 1.000000e+00, ptr [[P]], align 4
+; BE-MEMSSA-NEXT: br label %[[CONT]]
+; BE-MEMSSA: [[CONT]]:
+; BE-MEMSSA-NEXT: [[A:%.*]] = load i8, ptr [[P4]], align 1
+; BE-MEMSSA-NEXT: ret i8 [[A]]
;
%P4 = getelementptr i8, ptr %P, i32 2
br i1 %cond, label %T, label %F
@@ -475,18 +898,59 @@ Cont:
;; non-local i32 -> i8 partial redundancy load forwarding.
define i8 @coerce_offset_pre0(ptr %P, i1 %cond) {
-; CHECK-LABEL: @coerce_offset_pre0(
-; CHECK-NEXT: [[P4:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
-; CHECK-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
-; CHECK: T:
-; CHECK-NEXT: store i32 42, ptr [[P]], align 4
-; CHECK-NEXT: br label [[CONT:%.*]]
-; CHECK: F:
-; CHECK-NEXT: [[A_PRE:%.*]] = load i8, ptr [[P4]], align 1
-; CHECK-NEXT: br label [[CONT]]
-; CHECK: Cont:
-; CHECK-NEXT: [[A:%.*]] = phi i8 [ [[A_PRE]], [[F]] ], [ 0, [[T]] ]
-; CHECK-NEXT: ret i8 [[A]]
+; LE-MEMDEP-LABEL: define i8 @coerce_offset_pre0(
+; LE-MEMDEP-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; LE-MEMDEP-NEXT: [[P4:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; LE-MEMDEP-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; LE-MEMDEP: [[T]]:
+; LE-MEMDEP-NEXT: store i32 42, ptr [[P]], align 4
+; LE-MEMDEP-NEXT: br label %[[CONT:.*]]
+; LE-MEMDEP: [[F]]:
+; LE-MEMDEP-NEXT: [[A_PRE:%.*]] = load i8, ptr [[P4]], align 1
+; LE-MEMDEP-NEXT: br label %[[CONT]]
+; LE-MEMDEP: [[CONT]]:
+; LE-MEMDEP-NEXT: [[A:%.*]] = phi i8 [ [[A_PRE]], %[[F]] ], [ 0, %[[T]] ]
+; LE-MEMDEP-NEXT: ret i8 [[A]]
+;
+; LE-MEMSSA-LABEL: define i8 @coerce_offset_pre0(
+; LE-MEMSSA-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; LE-MEMSSA-NEXT: [[P4:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; LE-MEMSSA-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; LE-MEMSSA: [[T]]:
+; LE-MEMSSA-NEXT: store i32 42, ptr [[P]], align 4
+; LE-MEMSSA-NEXT: br label %[[CONT:.*]]
+; LE-MEMSSA: [[F]]:
+; LE-MEMSSA-NEXT: br label %[[CONT]]
+; LE-MEMSSA: [[CONT]]:
+; LE-MEMSSA-NEXT: [[A:%.*]] = load i8, ptr [[P4]], align 1
+; LE-MEMSSA-NEXT: ret i8 [[A]]
+;
+; BE-MEMDEP-LABEL: define i8 @coerce_offset_pre0(
+; BE-MEMDEP-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; BE-MEMDEP-NEXT: [[P4:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; BE-MEMDEP-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; BE-MEMDEP: [[T]]:
+; BE-MEMDEP-NEXT: store i32 42, ptr [[P]], align 4
+; BE-MEMDEP-NEXT: br label %[[CONT:.*]]
+; BE-MEMDEP: [[F]]:
+; BE-MEMDEP-NEXT: [[A_PRE:%.*]] = load i8, ptr [[P4]], align 1
+; BE-MEMDEP-NEXT: br label %[[CONT]]
+; BE-MEMDEP: [[CONT]]:
+; BE-MEMDEP-NEXT: [[A:%.*]] = phi i8 [ [[A_PRE]], %[[F]] ], [ 0, %[[T]] ]
+; BE-MEMDEP-NEXT: ret i8 [[A]]
+;
+; BE-MEMSSA-LABEL: define i8 @coerce_offset_pre0(
+; BE-MEMSSA-SAME: ptr [[P:%.*]], i1 [[COND:%.*]]) {
+; BE-MEMSSA-NEXT: [[P4:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; BE-MEMSSA-NEXT: br i1 [[COND]], label %[[T:.*]], label %[[F:.*]]
+; BE-MEMSSA: [[T]]:
+; BE-MEMSSA-NEXT: store i32 42, ptr [[P]], align 4
+; BE-MEMSSA-NEXT: br label %[[CONT:.*]]
+; BE-MEMSSA: [[F]]:
+; BE-MEMSSA-NEXT: br label %[[CONT]]
+; BE-MEMSSA: [[CONT]]:
+; BE-MEMSSA-NEXT: [[A:%.*]] = load i8, ptr [[P4]], align 1
+; BE-MEMSSA-NEXT: ret i8 [[A]]
;
%P4 = getelementptr i8, ptr %P, i32 2
br i1 %cond, label %T, label %F
@@ -504,20 +968,71 @@ Cont:
}
define i32 @chained_load(ptr %p, i32 %x, i32 %y) {
-; CHECK-LABEL: @chained_load(
-; CHECK-NEXT: block1:
-; CHECK-NEXT: [[A:%.*]] = alloca ptr, align 4
-; CHECK-NEXT: [[Z:%.*]] = load ptr, ptr [[P:%.*]], align 4
-; CHECK-NEXT: store ptr [[Z]], ptr [[A]], align 4
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: br i1 [[CMP]], label [[BLOCK2:%.*]], label [[BLOCK3:%.*]]
-; CHECK: block2:
-; CHECK-NEXT: br label [[BLOCK4:%.*]]
-; CHECK: block3:
-; CHECK-NEXT: br label [[BLOCK4]]
-; CHECK: block4:
-; CHECK-NEXT: [[D:%.*]] = load i32, ptr [[Z]], align 4
-; CHECK-NEXT: ret i32 [[D]]
+; LE-MEMDEP-LABEL: define i32 @chained_load(
+; LE-MEMDEP-SAME: ptr [[P:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]]) {
+; LE-MEMDEP-NEXT: [[BLOCK1:.*:]]
+; LE-MEMDEP-NEXT: [[A:%.*]] = alloca ptr, align 4
+; LE-MEMDEP-NEXT: [[Z:%.*]] = load ptr, ptr [[P]], align 4
+; LE-MEMDEP-NEXT: store ptr [[Z]], ptr [[A]], align 4
+; LE-MEMDEP-NEXT: [[CMP:%.*]] = icmp eq i32 [[X]], [[Y]]
+; LE-MEMDEP-NEXT: br i1 [[CMP]], label %[[BLOCK2:.*]], label %[[BLOCK3:.*]]
+; LE-MEMDEP: [[BLOCK2]]:
+; LE-MEMDEP-NEXT: br label %[[BLOCK4:.*]]
+; LE-MEMDEP: [[BLOCK3]]:
+; LE-MEMDEP-NEXT: br label %[[BLOCK4]]
+; LE-MEMDEP: [[BLOCK4]]:
+; LE-MEMDEP-NEXT: [[D:%.*]] = load i32, ptr [[Z]], align 4
+; LE-MEMDEP-NEXT: ret i32 [[D]]
+;
+; LE-MEMSSA-LABEL: define i32 @chained_load(
+; LE-MEMSSA-SAME: ptr [[P:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]]) {
+; LE-MEMSSA-NEXT: [[BLOCK1:.*:]]
+; LE-MEMSSA-NEXT: [[A:%.*]] = alloca ptr, align 4
+; LE-MEMSSA-NEXT: [[Z:%.*]] = load ptr, ptr [[P]], align 4
+; LE-MEMSSA-NEXT: store ptr [[Z]], ptr [[A]], align 4
+; LE-MEMSSA-NEXT: [[CMP:%.*]] = icmp eq i32 [[X]], [[Y]]
+; LE-MEMSSA-NEXT: br i1 [[CMP]], label %[[BLOCK2:.*]], label %[[BLOCK3:.*]]
+; LE-MEMSSA: [[BLOCK2]]:
+; LE-MEMSSA-NEXT: br label %[[BLOCK4:.*]]
+; LE-MEMSSA: [[BLOCK3]]:
+; LE-MEMSSA-NEXT: br label %[[BLOCK4]]
+; LE-MEMSSA: [[BLOCK4]]:
+; LE-MEMSSA-NEXT: [[C:%.*]] = load ptr, ptr [[P]], align 4
+; LE-MEMSSA-NEXT: [[D:%.*]] = load i32, ptr [[C]], align 4
+; LE-MEMSSA-NEXT: ret i32 [[D]]
+;
+; BE-MEMDEP-LABEL: define i32 @chained_load(
+; BE-MEMDEP-SAME: ptr [[P:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]]) {
+; BE-MEMDEP-NEXT: [[BLOCK1:.*:]]
+; BE-MEMDEP-NEXT: [[A:%.*]] = alloca ptr, align 4
+; BE-MEMDEP-NEXT: [[Z:%.*]] = load ptr, ptr [[P]], align 4
+; BE-MEMDEP-NEXT: store ptr [[Z]], ptr [[A]], align 4
+; BE-MEMDEP-NEXT: [[CMP:%.*]] = icmp eq i32 [[X]], [[Y]]
+; BE-MEMDEP-NEXT: br i1 [[CMP]], label %[[BLOCK2:.*]], label %[[BLOCK3:.*]]
+; BE-MEMDEP: [[BLOCK2]]:
+; BE-MEMDEP-NEXT: br label %[[BLOCK4:.*]]
+; BE-MEMDEP: [[BLOCK3]]:
+; BE-MEMDEP-NEXT: br label %[[BLOCK4]]
+; BE-MEMDEP: [[BLOCK4]]:
+; BE-MEMDEP-NEXT: [[D:%.*]] = load i32, ptr [[Z]], align 4
+; BE-MEMDEP-NEXT: ret i32 [[D]]
+;
+; BE-MEMSSA-LABEL: define i32 @chained_load(
+; BE-MEMSSA-SAME: ptr [[P:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]]) {
+; BE-MEMSSA-NEXT: [[BLOCK1:.*:]]
+; BE-MEMSSA-NEXT: [[A:%.*]] = alloca ptr, align 4
+; BE-MEMSSA-NEXT: [[Z:%.*]] = load ptr, ptr [[P]], align 4
+; BE-MEMSSA-NEXT: store ptr [[Z]], ptr [[A]], align 4
+; BE-MEMSSA-NEXT: [[CMP:%.*]] = icmp eq i32 [[X]], [[Y]]
+; BE-MEMSSA-NEXT: br i1 [[CMP]], label %[[BLOCK2:.*]], label %[[BLOCK3:.*]]
+; BE-MEMSSA: [[BLOCK2]]:
+; BE-MEMSSA-NEXT: br label %[[BLOCK4:.*]]
+; BE-MEMSSA: [[BLOCK3]]:
+; BE-MEMSSA-NEXT: br label %[[BLOCK4]]
+; BE-MEMSSA: [[BLOCK4]]:
+; BE-MEMSSA-NEXT: [[C:%.*]] = load ptr, ptr [[P]], align 4
+; BE-MEMSSA-NEXT: [[D:%.*]] = load i32, ptr [[C]], align 4
+; BE-MEMSSA-NEXT: ret i32 [[D]]
;
block1:
%A = alloca ptr
@@ -547,27 +1062,27 @@ declare i1 @cond() readonly
declare i1 @cond2() readonly
define i32 @phi_trans2() {
-; CHECK-LABEL: @phi_trans2(
-; CHECK-NEXT: entry:
+; CHECK-LABEL: define i32 @phi_trans2() {
+; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[P:%.*]] = alloca i32, i32 400, align 4
-; CHECK-NEXT: br label [[F1:%.*]]
-; CHECK: F1:
-; CHECK-NEXT: [[A:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ], [ 2, [[F:%.*]] ]
+; CHECK-NEXT: br label %[[F1:.*]]
+; CHECK: [[F1]]:
+; CHECK-NEXT: [[A:%.*]] = phi i32 [ 1, %[[ENTRY]] ], [ 2, %[[F:.*]] ]
; CHECK-NEXT: [[COND2:%.*]] = call i1 @cond()
-; CHECK-NEXT: br i1 [[COND2]], label [[T1:%.*]], label [[TY:%.*]]
-; CHECK: T1:
+; CHECK-NEXT: br i1 [[COND2]], label %[[T1:.*]], label %[[TY:.*]]
+; CHECK: [[T1]]:
; CHECK-NEXT: [[P2:%.*]] = getelementptr i32, ptr [[P]], i32 [[A]]
; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[P2]], align 4
; CHECK-NEXT: [[COND:%.*]] = call i1 @cond2()
-; CHECK-NEXT: br i1 [[COND]], label [[TX:%.*]], label [[F]]
-; CHECK: F:
+; CHECK-NEXT: br i1 [[COND]], label %[[TX:.*]], label %[[F]]
+; CHECK: [[F]]:
; CHECK-NEXT: [[P3:%.*]] = getelementptr i32, ptr [[P]], i32 2
; CHECK-NEXT: store i32 17, ptr [[P3]], align 4
; CHECK-NEXT: store i32 42, ptr [[P2]], align 4
-; CHECK-NEXT: br label [[F1]]
-; CHECK: TX:
+; CHECK-NEXT: br label %[[F1]]
+; CHECK: [[TX]]:
; CHECK-NEXT: ret i32 [[X]]
-; CHECK: TY:
+; CHECK: [[TY]]:
; CHECK-NEXT: ret i32 0
;
entry:
@@ -605,32 +1120,123 @@ TY:
}
define i32 @phi_trans3(ptr %p, i32 %x, i32 %y, i32 %z) {
-; CHECK-LABEL: @phi_trans3(
-; CHECK-NEXT: block1:
-; CHECK-NEXT: [[CMPXY:%.*]] = icmp eq i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: br i1 [[CMPXY]], label [[BLOCK2:%.*]], label [[BLOCK3:%.*]]
-; CHECK: block2:
-; CHECK-NEXT: store i32 87, ptr [[P:%.*]], align 4
-; CHECK-NEXT: br label [[BLOCK4:%.*]]
-; CHECK: block3:
-; CHECK-NEXT: [[P2:%.*]] = getelementptr i32, ptr [[P]], i32 43
-; CHECK-NEXT: store i32 97, ptr [[P2]], align 4
-; CHECK-NEXT: br label [[BLOCK4]]
-; CHECK: block4:
-; CHECK-NEXT: [[D:%.*]] = phi i32 [ 87, [[BLOCK2]] ], [ 97, [[BLOCK3]] ]
-; CHECK-NEXT: br i1 [[CMPXY]], label [[BLOCK5:%.*]], label [[EXIT:%.*]]
-; CHECK: block5:
-; CHECK-NEXT: br i1 true, label [[BLOCK6:%.*]], label [[BLOCK5_EXIT_CRIT_EDGE:%.*]]
-; CHECK: block5.exit_crit_edge:
-; CHECK-NEXT: br label [[EXIT]]
-; CHECK: block6:
-; CHECK-NEXT: br i1 true, label [[BLOCK7:%.*]], label [[BLOCK6_EXIT_CRIT_EDGE:%.*]]
-; CHECK: block6.exit_crit_edge:
-; CHECK-NEXT: br label [[EXIT]]
-; CHECK: block7:
-; CHECK-NEXT: ret i32 [[D]]
-; CHECK: exit:
-; CHECK-NEXT: ret i32 -1
+; LE-MEMDEP-LABEL: define i32 @phi_trans3(
+; LE-MEMDEP-SAME: ptr [[P:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]]) {
+; LE-MEMDEP-NEXT: [[BLOCK1:.*:]]
+; LE-MEMDEP-NEXT: [[CMPXY:%.*]] = icmp eq i32 [[X]], [[Y]]
+; LE-MEMDEP-NEXT: br i1 [[CMPXY]], label %[[BLOCK2:.*]], label %[[BLOCK3:.*]]
+; LE-MEMDEP: [[BLOCK2]]:
+; LE-MEMDEP-NEXT: store i32 87, ptr [[P]], align 4
+; LE-MEMDEP-NEXT: br label %[[BLOCK4:.*]]
+; LE-MEMDEP: [[BLOCK3]]:
+; LE-MEMDEP-NEXT: [[P2:%.*]] = getelementptr i32, ptr [[P]], i32 43
+; LE-MEMDEP-NEXT: store i32 97, ptr [[P2]], align 4
+; LE-MEMDEP-NEXT: br label %[[BLOCK4]]
+; LE-MEMDEP: [[BLOCK4]]:
+; LE-MEMDEP-NEXT: [[D:%.*]] = phi i32 [ 87, %[[BLOCK2]] ], [ 97, %[[BLOCK3]] ]
+; LE-MEMDEP-NEXT: br i1 [[CMPXY]], label %[[BLOCK5:.*]], label %[[EXIT:.*]]
+; LE-MEMDEP: [[BLOCK5]]:
+; LE-MEMDEP-NEXT: br i1 true, label %[[BLOCK6:.*]], label %[[BLOCK5_EXIT_CRIT_EDGE:.*]]
+; LE-MEMDEP: [[BLOCK5_EXIT_CRIT_EDGE]]:
+; LE-MEMDEP-NEXT: br label %[[EXIT]]
+; LE-MEMDEP: [[BLOCK6]]:
+; LE-MEMDEP-NEXT: br i1 true, label %[[BLOCK7:.*]], label %[[BLOCK6_EXIT_CRIT_EDGE:.*]]
+; LE-MEMDEP: [[BLOCK6_EXIT_CRIT_EDGE]]:
+; LE-MEMDEP-NEXT: br label %[[EXIT]]
+; LE-MEMDEP: [[BLOCK7]]:
+; LE-MEMDEP-NEXT: ret i32 [[D]]
+; LE-MEMDEP: [[EXIT]]:
+; LE-MEMDEP-NEXT: ret i32 -1
+;
+; LE-MEMSSA-LABEL: define i32 @phi_trans3(
+; LE-MEMSSA-SAME: ptr [[P:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]]) {
+; LE-MEMSSA-NEXT: [[BLOCK1:.*:]]
+; LE-MEMSSA-NEXT: [[CMPXY:%.*]] = icmp eq i32 [[X]], [[Y]]
+; LE-MEMSSA-NEXT: br i1 [[CMPXY]], label %[[BLOCK2:.*]], label %[[BLOCK3:.*]]
+; LE-MEMSSA: [[BLOCK2]]:
+; LE-MEMSSA-NEXT: store i32 87, ptr [[P]], align 4
+; LE-MEMSSA-NEXT: br label %[[BLOCK4:.*]]
+; LE-MEMSSA: [[BLOCK3]]:
+; LE-MEMSSA-NEXT: [[P2:%.*]] = getelementptr i32, ptr [[P]], i32 43
+; LE-MEMSSA-NEXT: store i32 97, ptr [[P2]], align 4
+; LE-MEMSSA-NEXT: br label %[[BLOCK4]]
+; LE-MEMSSA: [[BLOCK4]]:
+; LE-MEMSSA-NEXT: [[A:%.*]] = phi i32 [ -1, %[[BLOCK2]] ], [ 42, %[[BLOCK3]] ]
+; LE-MEMSSA-NEXT: br i1 [[CMPXY]], label %[[BLOCK5:.*]], label %[[EXIT:.*]]
+; LE-MEMSSA: [[BLOCK5]]:
+; LE-MEMSSA-NEXT: [[B:%.*]] = add i32 [[A]], 1
+; LE-MEMSSA-NEXT: br i1 true, label %[[BLOCK6:.*]], label %[[BLOCK5_EXIT_CRIT_EDGE:.*]]
+; LE-MEMSSA: [[BLOCK5_EXIT_CRIT_EDGE]]:
+; LE-MEMSSA-NEXT: br label %[[EXIT]]
+; LE-MEMSSA: [[BLOCK6]]:
+; LE-MEMSSA-NEXT: [[C:%.*]] = getelementptr i32, ptr [[P]], i32 [[B]]
+; LE-MEMSSA-NEXT: br i1 true, label %[[BLOCK7:.*]], label %[[BLOCK6_EXIT_CRIT_EDGE:.*]]
+; LE-MEMSSA: [[BLOCK6_EXIT_CRIT_EDGE]]:
+; LE-MEMSSA-NEXT: br label %[[EXIT]]
+; LE-MEMSSA: [[BLOCK7]]:
+; LE-MEMSSA-NEXT: [[D:%.*]] = load i32, ptr [[C]], align 4
+; LE-MEMSSA-NEXT: ret i32 [[D]]
+; LE-MEMSSA: [[EXIT]]:
+; LE-MEMSSA-NEXT: ret i32 -1
+;
+; BE-MEMDEP-LABEL: define i32 @phi_trans3(
+; BE-MEMDEP-SAME: ptr [[P:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]]) {
+; BE-MEMDEP-NEXT: [[BLOCK1:.*:]]
+; BE-MEMDEP-NEXT: [[CMPXY:%.*]] = icmp eq i32 [[X]], [[Y]]
+; BE-MEMDEP-NEXT: br i1 [[CMPXY]], label %[[BLOCK2:.*]], label %[[BLOCK3:.*]]
+; BE-MEMDEP: [[BLOCK2]]:
+; BE-MEMDEP-NEXT: store i32 87, ptr [[P]], align 4
+; BE-MEMDEP-NEXT: br label %[[BLOCK4:.*]]
+; BE-MEMDEP: [[BLOCK3]]:
+; BE-MEMDEP-NEXT: [[P2:%.*]] = getelementptr i32, ptr [[P]], i32 43
+; BE-MEMDEP-NEXT: store i32 97, ptr [[P2]], align 4
+; BE-MEMDEP-NEXT: br label %[[BLOCK4]]
+; BE-MEMDEP: [[BLOCK4]]:
+; BE-MEMDEP-NEXT: [[D:%.*]] = phi i32 [ 87, %[[BLOCK2]] ], [ 97, %[[BLOCK3]] ]
+; BE-MEMDEP-NEXT: br i1 [[CMPXY]], label %[[BLOCK5:.*]], label %[[EXIT:.*]]
+; BE-MEMDEP: [[BLOCK5]]:
+; BE-MEMDEP-NEXT: br i1 true, label %[[BLOCK6:.*]], label %[[BLOCK5_EXIT_CRIT_EDGE:.*]]
+; BE-MEMDEP: [[BLOCK5_EXIT_CRIT_EDGE]]:
+; BE-MEMDEP-NEXT: br label %[[EXIT]]
+; BE-MEMDEP: [[BLOCK6]]:
+; BE-MEMDEP-NEXT: br i1 true, label %[[BLOCK7:.*]], label %[[BLOCK6_EXIT_CRIT_EDGE:.*]]
+; BE-MEMDEP: [[BLOCK6_EXIT_CRIT_EDGE]]:
+; BE-MEMDEP-NEXT: br label %[[EXIT]]
+; BE-MEMDEP: [[BLOCK7]]:
+; BE-MEMDEP-NEXT: ret i32 [[D]]
+; BE-MEMDEP: [[EXIT]]:
+; BE-MEMDEP-NEXT: ret i32 -1
+;
+; BE-MEMSSA-LABEL: define i32 @phi_trans3(
+; BE-MEMSSA-SAME: ptr [[P:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]]) {
+; BE-MEMSSA-NEXT: [[BLOCK1:.*:]]
+; BE-MEMSSA-NEXT: [[CMPXY:%.*]] = icmp eq i32 [[X]], [[Y]]
+; BE-MEMSSA-NEXT: br i1 [[CMPXY]], label %[[BLOCK2:.*]], label %[[BLOCK3:.*]]
+; BE-MEMSSA: [[BLOCK2]]:
+; BE-MEMSSA-NEXT: store i32 87, ptr [[P]], align 4
+; BE-MEMSSA-NEXT: br label %[[BLOCK4:.*]]
+; BE-MEMSSA: [[BLOCK3]]:
+; BE-MEMSSA-NEXT: [[P2:%.*]] = getelementptr i32, ptr [[P]], i32 43
+; BE-MEMSSA-NEXT: store i32 97, ptr [[P2]], align 4
+; BE-MEMSSA-NEXT: br label %[[BLOCK4]]
+; BE-MEMSSA: [[BLOCK4]]:
+; BE-MEMSSA-NEXT: [[A:%.*]] = phi i32 [ -1, %[[BLOCK2]] ], [ 42, %[[BLOCK3]] ]
+; BE-MEMSSA-NEXT: br i1 [[CMPXY]], label %[[BLOCK5:.*]], label %[[EXIT:.*]]
+; BE-MEMSSA: [[BLOCK5]]:
+; BE-MEMSSA-NEXT: [[B:%.*]] = add i32 [[A]], 1
+; BE-MEMSSA-NEXT: br i1 true, label %[[BLOCK6:.*]], label %[[BLOCK5_EXIT_CRIT_EDGE:.*]]
+; BE-MEMSSA: [[BLOCK5_EXIT_CRIT_EDGE]]:
+; BE-MEMSSA-NEXT: br label %[[EXIT]]
+; BE-MEMSSA: [[BLOCK6]]:
+; BE-MEMSSA-NEXT: [[C:%.*]] = getelementptr i32, ptr [[P]], i32 [[B]]
+; BE-MEMSSA-NEXT: br i1 true, label %[[BLOCK7:.*]], label %[[BLOCK6_EXIT_CRIT_EDGE:.*]]
+; BE-MEMSSA: [[BLOCK6_EXIT_CRIT_EDGE]]:
+; BE-MEMSSA-NEXT: br label %[[EXIT]]
+; BE-MEMSSA: [[BLOCK7]]:
+; BE-MEMSSA-NEXT: [[D:%.*]] = load i32, ptr [[C]], align 4
+; BE-MEMSSA-NEXT: ret i32 [[D]]
+; BE-MEMSSA: [[EXIT]]:
+; BE-MEMSSA-NEXT: ret i32 -1
;
block1:
%cmpxy = icmp eq i32 %x, %y
@@ -668,21 +1274,77 @@ exit:
}
define i8 @phi_trans4(ptr %p) {
-; CHECK-LABEL: @phi_trans4(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[X3:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 192
-; CHECK-NEXT: store i8 -64, ptr [[X3]], align 1
-; CHECK-NEXT: [[X:%.*]] = getelementptr i8, ptr [[P]], i32 4
-; CHECK-NEXT: [[Y2_PRE:%.*]] = load i8, ptr [[X]], align 1
-; CHECK-NEXT: br label [[LOOP:%.*]]
-; CHECK: loop:
-; CHECK-NEXT: [[Y2:%.*]] = phi i8 [ [[Y2_PRE]], [[ENTRY:%.*]] ], [ 0, [[LOOP]] ]
-; CHECK-NEXT: [[COND:%.*]] = call i1 @cond2()
-; CHECK-NEXT: store i32 0, ptr [[X3]], align 4
-; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[OUT:%.*]]
-; CHECK: out:
-; CHECK-NEXT: [[R:%.*]] = add i8 [[Y2_PRE]], [[Y2]]
-; CHECK-NEXT: ret i8 [[R]]
+; LE-MEMDEP-LABEL: define i8 @phi_trans4(
+; LE-MEMDEP-SAME: ptr [[P:%.*]]) {
+; LE-MEMDEP-NEXT: [[ENTRY:.*]]:
+; LE-MEMDEP-NEXT: [[X3:%.*]] = getelementptr i8, ptr [[P]], i32 192
+; LE-MEMDEP-NEXT: store i8 -64, ptr [[X3]], align 1
+; LE-MEMDEP-NEXT: [[X:%.*]] = getelementptr i8, ptr [[P]], i32 4
+; LE-MEMDEP-NEXT: [[Y:%.*]] = load i8, ptr [[X]], align 1
+; LE-MEMDEP-NEXT: br label %[[LOOP:.*]]
+; LE-MEMDEP: [[LOOP]]:
+; LE-MEMDEP-NEXT: [[Y2:%.*]] = phi i8 [ [[Y]], %[[ENTRY]] ], [ 0, %[[LOOP]] ]
+; LE-MEMDEP-NEXT: [[COND:%.*]] = call i1 @cond2()
+; LE-MEMDEP-NEXT: store i32 0, ptr [[X3]], align 4
+; LE-MEMDEP-NEXT: br i1 [[COND]], label %[[LOOP]], label %[[OUT:.*]]
+; LE-MEMDEP: [[OUT]]:
+; LE-MEMDEP-NEXT: [[R:%.*]] = add i8 [[Y]], [[Y2]]
+; LE-MEMDEP-NEXT: ret i8 [[R]]
+;
+; LE-MEMSSA-LABEL: define i8 @phi_trans4(
+; LE-MEMSSA-SAME: ptr [[P:%.*]]) {
+; LE-MEMSSA-NEXT: [[ENTRY:.*]]:
+; LE-MEMSSA-NEXT: [[X3:%.*]] = getelementptr i8, ptr [[P]], i32 192
+; LE-MEMSSA-NEXT: store i8 -64, ptr [[X3]], align 1
+; LE-MEMSSA-NEXT: [[X:%.*]] = getelementptr i8, ptr [[P]], i32 4
+; LE-MEMSSA-NEXT: [[Y:%.*]] = load i8, ptr [[X]], align 1
+; LE-MEMSSA-NEXT: br label %[[LOOP:.*]]
+; LE-MEMSSA: [[LOOP]]:
+; LE-MEMSSA-NEXT: [[I:%.*]] = phi i32 [ 4, %[[ENTRY]] ], [ 192, %[[LOOP]] ]
+; LE-MEMSSA-NEXT: [[X2:%.*]] = getelementptr i8, ptr [[P]], i32 [[I]]
+; LE-MEMSSA-NEXT: [[Y2:%.*]] = load i8, ptr [[X2]], align 1
+; LE-MEMSSA-NEXT: [[COND:%.*]] = call i1 @cond2()
+; LE-MEMSSA-NEXT: store i32 0, ptr [[X3]], align 4
+; LE-MEMSSA-NEXT: br i1 [[COND]], label %[[LOOP]], label %[[OUT:.*]]
+; LE-MEMSSA: [[OUT]]:
+; LE-MEMSSA-NEXT: [[R:%.*]] = add i8 [[Y]], [[Y2]]
+; LE-MEMSSA-NEXT: ret i8 [[R]]
+;
+; BE-MEMDEP-LABEL: define i8 @phi_trans4(
+; BE-MEMDEP-SAME: ptr [[P:%.*]]) {
+; BE-MEMDEP-NEXT: [[ENTRY:.*]]:
+; BE-MEMDEP-NEXT: [[X3:%.*]] = getelementptr i8, ptr [[P]], i32 192
+; BE-MEMDEP-NEXT: store i8 -64, ptr [[X3]], align 1
+; BE-MEMDEP-NEXT: [[X:%.*]] = getelementptr i8, ptr [[P]], i32 4
+; BE-MEMDEP-NEXT: [[Y:%.*]] = load i8, ptr [[X]], align 1
+; BE-MEMDEP-NEXT: br label %[[LOOP:.*]]
+; BE-MEMDEP: [[LOOP]]:
+; BE-MEMDEP-NEXT: [[Y2:%.*]] = phi i8 [ [[Y]], %[[ENTRY]] ], [ 0, %[[LOOP]] ]
+; BE-MEMDEP-NEXT: [[COND:%.*]] = call i1 @cond2()
+; BE-MEMDEP-NEXT: store i32 0, ptr [[X3]], align 4
+; BE-MEMDEP-NEXT: br i1 [[COND]], label %[[LOOP]], label %[[OUT:.*]]
+; BE-MEMDEP: [[OUT]]:
+; BE-MEMDEP-NEXT: [[R:%.*]] = add i8 [[Y]], [[Y2]]
+; BE-MEMDEP-NEXT: ret i8 [[R]]
+;
+; BE-MEMSSA-LABEL: define i8 @phi_trans4(
+; BE-MEMSSA-SAME: ptr [[P:%.*]]) {
+; BE-MEMSSA-NEXT: [[ENTRY:.*]]:
+; BE-MEMSSA-NEXT: [[X3:%.*]] = getelementptr i8, ptr [[P]], i32 192
+; BE-MEMSSA-NEXT: store i8 -64, ptr [[X3]], align 1
+; BE-MEMSSA-NEXT: [[X:%.*]] = getelementptr i8, ptr [[P]], i32 4
+; BE-MEMSSA-NEXT: [[Y:%.*]] = load i8, ptr [[X]], align 1
+; BE-MEMSSA-NEXT: br label %[[LOOP:.*]]
+; BE-MEMSSA: [[LOOP]]:
+; BE-MEMSSA-NEXT: [[I:%.*]] = phi i32 [ 4, %[[ENTRY]] ], [ 192, %[[LOOP]] ]
+; BE-MEMSSA-NEXT: [[X2:%.*]] = getelementptr i8, ptr [[P]], i32 [[I]]
+; BE-MEMSSA-NEXT: [[Y2:%.*]] = load i8, ptr [[X2]], align 1
+; BE-MEMSSA-NEXT: [[COND:%.*]] = call i1 @cond2()
+; BE-MEMSSA-NEXT: store i32 0, ptr [[X3]], align 4
+; BE-MEMSSA-NEXT: br i1 [[COND]], label %[[LOOP]], label %[[OUT:.*]]
+; BE-MEMSSA: [[OUT]]:
+; BE-MEMSSA-NEXT: [[R:%.*]] = add i8 [[Y]], [[Y2]]
+; BE-MEMSSA-NEXT: ret i8 [[R]]
;
entry:
%X3 = getelementptr i8, ptr %p, i32 192
@@ -709,28 +1371,97 @@ out:
}
define i8 @phi_trans5(ptr %p) {
-; CHECK-LABEL: @phi_trans5(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[X4:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
-; CHECK-NEXT: store i8 19, ptr [[X4]], align 1
-; CHECK-NEXT: [[X:%.*]] = getelementptr i8, ptr [[P]], i32 4
-; CHECK-NEXT: [[Y:%.*]] = load i8, ptr [[X]], align 1
-; CHECK-NEXT: br label [[LOOP:%.*]]
-; CHECK: loop:
-; CHECK-NEXT: [[Y2:%.*]] = phi i8 [ [[Y]], [[ENTRY:%.*]] ], [ [[Y2_PRE:%.*]], [[CONT:%.*]] ]
-; CHECK-NEXT: [[I:%.*]] = phi i32 [ 4, [[ENTRY]] ], [ 3, [[CONT]] ]
-; CHECK-NEXT: [[X2:%.*]] = getelementptr i8, ptr [[P]], i32 [[I]]
-; CHECK-NEXT: [[COND:%.*]] = call i1 @cond2()
-; CHECK-NEXT: br i1 [[COND]], label [[CONT]], label [[OUT:%.*]]
-; CHECK: cont:
-; CHECK-NEXT: [[Z:%.*]] = getelementptr i8, ptr [[X2]], i32 -1
-; CHECK-NEXT: store i32 50462976, ptr [[Z]], align 4
-; CHECK-NEXT: [[X2_PHI_TRANS_INSERT:%.*]] = getelementptr i8, ptr [[P]], i32 3
-; CHECK-NEXT: [[Y2_PRE]] = load i8, ptr [[X2_PHI_TRANS_INSERT]], align 1
-; CHECK-NEXT: br label [[LOOP]]
-; CHECK: out:
-; CHECK-NEXT: [[R:%.*]] = add i8 [[Y]], [[Y2]]
-; CHECK-NEXT: ret i8 [[R]]
+; LE-MEMDEP-LABEL: define i8 @phi_trans5(
+; LE-MEMDEP-SAME: ptr [[P:%.*]]) {
+; LE-MEMDEP-NEXT: [[ENTRY:.*]]:
+; LE-MEMDEP-NEXT: [[X4:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; LE-MEMDEP-NEXT: store i8 19, ptr [[X4]], align 1
+; LE-MEMDEP-NEXT: [[X:%.*]] = getelementptr i8, ptr [[P]], i32 4
+; LE-MEMDEP-NEXT: [[Y:%.*]] = load i8, ptr [[X]], align 1
+; LE-MEMDEP-NEXT: br label %[[LOOP:.*]]
+; LE-MEMDEP: [[LOOP]]:
+; LE-MEMDEP-NEXT: [[Y2:%.*]] = phi i8 [ [[Y]], %[[ENTRY]] ], [ [[Y2_PRE:%.*]], %[[CONT:.*]] ]
+; LE-MEMDEP-NEXT: [[I:%.*]] = phi i32 [ 4, %[[ENTRY]] ], [ 3, %[[CONT]] ]
+; LE-MEMDEP-NEXT: [[X2:%.*]] = getelementptr i8, ptr [[P]], i32 [[I]]
+; LE-MEMDEP-NEXT: [[COND:%.*]] = call i1 @cond2()
+; LE-MEMDEP-NEXT: br i1 [[COND]], label %[[CONT]], label %[[OUT:.*]]
+; LE-MEMDEP: [[CONT]]:
+; LE-MEMDEP-NEXT: [[Z:%.*]] = getelementptr i8, ptr [[X2]], i32 -1
+; LE-MEMDEP-NEXT: store i32 50462976, ptr [[Z]], align 4
+; LE-MEMDEP-NEXT: [[X2_PHI_TRANS_INSERT:%.*]] = getelementptr i8, ptr [[P]], i32 3
+; LE-MEMDEP-NEXT: [[Y2_PRE]] = load i8, ptr [[X2_PHI_TRANS_INSERT]], align 1
+; LE-MEMDEP-NEXT: br label %[[LOOP]]
+; LE-MEMDEP: [[OUT]]:
+; LE-MEMDEP-NEXT: [[R:%.*]] = add i8 [[Y]], [[Y2]]
+; LE-MEMDEP-NEXT: ret i8 [[R]]
+;
+; LE-MEMSSA-LABEL: define i8 @phi_trans5(
+; LE-MEMSSA-SAME: ptr [[P:%.*]]) {
+; LE-MEMSSA-NEXT: [[ENTRY:.*]]:
+; LE-MEMSSA-NEXT: [[X4:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; LE-MEMSSA-NEXT: store i8 19, ptr [[X4]], align 1
+; LE-MEMSSA-NEXT: [[X:%.*]] = getelementptr i8, ptr [[P]], i32 4
+; LE-MEMSSA-NEXT: [[Y:%.*]] = load i8, ptr [[X]], align 1
+; LE-MEMSSA-NEXT: br label %[[LOOP:.*]]
+; LE-MEMSSA: [[LOOP]]:
+; LE-MEMSSA-NEXT: [[I:%.*]] = phi i32 [ 4, %[[ENTRY]] ], [ 3, %[[CONT:.*]] ]
+; LE-MEMSSA-NEXT: [[X2:%.*]] = getelementptr i8, ptr [[P]], i32 [[I]]
+; LE-MEMSSA-NEXT: [[Y2:%.*]] = load i8, ptr [[X2]], align 1
+; LE-MEMSSA-NEXT: [[COND:%.*]] = call i1 @cond2()
+; LE-MEMSSA-NEXT: br i1 [[COND]], label %[[CONT]], label %[[OUT:.*]]
+; LE-MEMSSA: [[CONT]]:
+; LE-MEMSSA-NEXT: [[Z:%.*]] = getelementptr i8, ptr [[X2]], i32 -1
+; LE-MEMSSA-NEXT: store i32 50462976, ptr [[Z]], align 4
+; LE-MEMSSA-NEXT: br label %[[LOOP]]
+; LE-MEMSSA: [[OUT]]:
+; LE-MEMSSA-NEXT: [[R:%.*]] = add i8 [[Y]], [[Y2]]
+; LE-MEMSSA-NEXT: ret i8 [[R]]
+;
+; BE-MEMDEP-LABEL: define i8 @phi_trans5(
+; BE-MEMDEP-SAME: ptr [[P:%.*]]) {
+; BE-MEMDEP-NEXT: [[ENTRY:.*]]:
+; BE-MEMDEP-NEXT: [[X4:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; BE-MEMDEP-NEXT: store i8 19, ptr [[X4]], align 1
+; BE-MEMDEP-NEXT: [[X:%.*]] = getelementptr i8, ptr [[P]], i32 4
+; BE-MEMDEP-NEXT: [[Y:%.*]] = load i8, ptr [[X]], align 1
+; BE-MEMDEP-NEXT: br label %[[LOOP:.*]]
+; BE-MEMDEP: [[LOOP]]:
+; BE-MEMDEP-NEXT: [[Y2:%.*]] = phi i8 [ [[Y]], %[[ENTRY]] ], [ [[Y2_PRE:%.*]], %[[CONT:.*]] ]
+; BE-MEMDEP-NEXT: [[I:%.*]] = phi i32 [ 4, %[[ENTRY]] ], [ 3, %[[CONT]] ]
+; BE-MEMDEP-NEXT: [[X2:%.*]] = getelementptr i8, ptr [[P]], i32 [[I]]
+; BE-MEMDEP-NEXT: [[COND:%.*]] = call i1 @cond2()
+; BE-MEMDEP-NEXT: br i1 [[COND]], label %[[CONT]], label %[[OUT:.*]]
+; BE-MEMDEP: [[CONT]]:
+; BE-MEMDEP-NEXT: [[Z:%.*]] = getelementptr i8, ptr [[X2]], i32 -1
+; BE-MEMDEP-NEXT: store i32 50462976, ptr [[Z]], align 4
+; BE-MEMDEP-NEXT: [[X2_PHI_TRANS_INSERT:%.*]] = getelementptr i8, ptr [[P]], i32 3
+; BE-MEMDEP-NEXT: [[Y2_PRE]] = load i8, ptr [[X2_PHI_TRANS_INSERT]], align 1
+; BE-MEMDEP-NEXT: br label %[[LOOP]]
+; BE-MEMDEP: [[OUT]]:
+; BE-MEMDEP-NEXT: [[R:%.*]] = add i8 [[Y]], [[Y2]]
+; BE-MEMDEP-NEXT: ret i8 [[R]]
+;
+; BE-MEMSSA-LABEL: define i8 @phi_trans5(
+; BE-MEMSSA-SAME: ptr [[P:%.*]]) {
+; BE-MEMSSA-NEXT: [[ENTRY:.*]]:
+; BE-MEMSSA-NEXT: [[X4:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; BE-MEMSSA-NEXT: store i8 19, ptr [[X4]], align 1
+; BE-MEMSSA-NEXT: [[X:%.*]] = getelementptr i8, ptr [[P]], i32 4
+; BE-MEMSSA-NEXT: [[Y:%.*]] = load i8, ptr [[X]], align 1
+; BE-MEMSSA-NEXT: br label %[[LOOP:.*]]
+; BE-MEMSSA: [[LOOP]]:
+; BE-MEMSSA-NEXT: [[I:%.*]] = phi i32 [ 4, %[[ENTRY]] ], [ 3, %[[CONT:.*]] ]
+; BE-MEMSSA-NEXT: [[X2:%.*]] = getelementptr i8, ptr [[P]], i32 [[I]]
+; BE-MEMSSA-NEXT: [[Y2:%.*]] = load i8, ptr [[X2]], align 1
+; BE-MEMSSA-NEXT: [[COND:%.*]] = call i1 @cond2()
+; BE-MEMSSA-NEXT: br i1 [[COND]], label %[[CONT]], label %[[OUT:.*]]
+; BE-MEMSSA: [[CONT]]:
+; BE-MEMSSA-NEXT: [[Z:%.*]] = getelementptr i8, ptr [[X2]], i32 -1
+; BE-MEMSSA-NEXT: store i32 50462976, ptr [[Z]], align 4
+; BE-MEMSSA-NEXT: br label %[[LOOP]]
+; BE-MEMSSA: [[OUT]]:
+; BE-MEMSSA-NEXT: [[R:%.*]] = add i8 [[Y]], [[Y2]]
+; BE-MEMSSA-NEXT: ret i8 [[R]]
;
entry:
@@ -766,24 +1497,79 @@ declare void @use_i32(i32) readonly
; into header. Make sure we translate the address for %l1 correctly where
; parts of the address computations are in
diff erent basic blocks.
define i32 @phi_trans6(ptr noalias nocapture readonly %x, i1 %cond) {
-; CHECK-LABEL: @phi_trans6(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[L0:%.*]] = load i32, ptr [[X:%.*]], align 4
-; CHECK-NEXT: call void @use_i32(i32 [[L0]])
-; CHECK-NEXT: br label [[HEADER:%.*]]
-; CHECK: header:
-; CHECK-NEXT: [[L1_PRE:%.*]] = phi i32 [ [[L0]], [[ENTRY:%.*]] ], [ [[L1_PRE1:%.*]], [[LATCH_HEADER_CRIT_EDGE:%.*]] ]
-; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[IV_NEXT:%.*]], [[LATCH_HEADER_CRIT_EDGE]] ]
-; CHECK-NEXT: indirectbr ptr blockaddress(@phi_trans6, [[LATCH:%.*]]), [label %latch]
-; CHECK: latch:
-; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
-; CHECK-NEXT: br i1 [[COND:%.*]], label [[EXIT:%.*]], label [[LATCH_HEADER_CRIT_EDGE]]
-; CHECK: latch.header_crit_edge:
-; CHECK-NEXT: [[GEP_1_PHI_TRANS_INSERT_PHI_TRANS_INSERT:%.*]] = getelementptr i32, ptr [[X]], i32 [[IV_NEXT]]
-; CHECK-NEXT: [[L1_PRE1]] = load i32, ptr [[GEP_1_PHI_TRANS_INSERT_PHI_TRANS_INSERT]], align 4
-; CHECK-NEXT: br label [[HEADER]]
-; CHECK: exit:
-; CHECK-NEXT: ret i32 [[L1_PRE]]
+; LE-MEMDEP-LABEL: define i32 @phi_trans6(
+; LE-MEMDEP-SAME: ptr noalias readonly captures(none) [[X:%.*]], i1 [[COND:%.*]]) {
+; LE-MEMDEP-NEXT: [[ENTRY:.*]]:
+; LE-MEMDEP-NEXT: [[L0:%.*]] = load i32, ptr [[X]], align 4
+; LE-MEMDEP-NEXT: call void @use_i32(i32 [[L0]])
+; LE-MEMDEP-NEXT: br label %[[HEADER:.*]]
+; LE-MEMDEP: [[HEADER]]:
+; LE-MEMDEP-NEXT: [[L1:%.*]] = phi i32 [ [[L0]], %[[ENTRY]] ], [ [[L1_PRE:%.*]], %[[LATCH_HEADER_CRIT_EDGE:.*]] ]
+; LE-MEMDEP-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH_HEADER_CRIT_EDGE]] ]
+; LE-MEMDEP-NEXT: indirectbr ptr blockaddress(@phi_trans6, %[[LATCH:.*]]), [label %latch]
+; LE-MEMDEP: [[LATCH]]:
+; LE-MEMDEP-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; LE-MEMDEP-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LATCH_HEADER_CRIT_EDGE]]
+; LE-MEMDEP: [[LATCH_HEADER_CRIT_EDGE]]:
+; LE-MEMDEP-NEXT: [[GEP_1_PHI_TRANS_INSERT_PHI_TRANS_INSERT:%.*]] = getelementptr i32, ptr [[X]], i32 [[IV_NEXT]]
+; LE-MEMDEP-NEXT: [[L1_PRE]] = load i32, ptr [[GEP_1_PHI_TRANS_INSERT_PHI_TRANS_INSERT]], align 4
+; LE-MEMDEP-NEXT: br label %[[HEADER]]
+; LE-MEMDEP: [[EXIT]]:
+; LE-MEMDEP-NEXT: ret i32 [[L1]]
+;
+; LE-MEMSSA-LABEL: define i32 @phi_trans6(
+; LE-MEMSSA-SAME: ptr noalias readonly captures(none) [[X:%.*]], i1 [[COND:%.*]]) {
+; LE-MEMSSA-NEXT: [[ENTRY:.*]]:
+; LE-MEMSSA-NEXT: [[L0:%.*]] = load i32, ptr [[X]], align 4
+; LE-MEMSSA-NEXT: call void @use_i32(i32 [[L0]])
+; LE-MEMSSA-NEXT: br label %[[HEADER:.*]]
+; LE-MEMSSA: [[HEADER]]:
+; LE-MEMSSA-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
+; LE-MEMSSA-NEXT: indirectbr ptr blockaddress(@phi_trans6, %[[LATCH]]), [label %latch]
+; LE-MEMSSA: [[LATCH]]:
+; LE-MEMSSA-NEXT: [[GEP_1:%.*]] = getelementptr i32, ptr [[X]], i32 [[IV]]
+; LE-MEMSSA-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_1]], align 4
+; LE-MEMSSA-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; LE-MEMSSA-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[HEADER]]
+; LE-MEMSSA: [[EXIT]]:
+; LE-MEMSSA-NEXT: ret i32 [[L1]]
+;
+; BE-MEMDEP-LABEL: define i32 @phi_trans6(
+; BE-MEMDEP-SAME: ptr noalias readonly captures(none) [[X:%.*]], i1 [[COND:%.*]]) {
+; BE-MEMDEP-NEXT: [[ENTRY:.*]]:
+; BE-MEMDEP-NEXT: [[L0:%.*]] = load i32, ptr [[X]], align 4
+; BE-MEMDEP-NEXT: call void @use_i32(i32 [[L0]])
+; BE-MEMDEP-NEXT: br label %[[HEADER:.*]]
+; BE-MEMDEP: [[HEADER]]:
+; BE-MEMDEP-NEXT: [[L1:%.*]] = phi i32 [ [[L0]], %[[ENTRY]] ], [ [[L1_PRE:%.*]], %[[LATCH_HEADER_CRIT_EDGE:.*]] ]
+; BE-MEMDEP-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH_HEADER_CRIT_EDGE]] ]
+; BE-MEMDEP-NEXT: indirectbr ptr blockaddress(@phi_trans6, %[[LATCH:.*]]), [label %latch]
+; BE-MEMDEP: [[LATCH]]:
+; BE-MEMDEP-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; BE-MEMDEP-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LATCH_HEADER_CRIT_EDGE]]
+; BE-MEMDEP: [[LATCH_HEADER_CRIT_EDGE]]:
+; BE-MEMDEP-NEXT: [[GEP_1_PHI_TRANS_INSERT_PHI_TRANS_INSERT:%.*]] = getelementptr i32, ptr [[X]], i32 [[IV_NEXT]]
+; BE-MEMDEP-NEXT: [[L1_PRE]] = load i32, ptr [[GEP_1_PHI_TRANS_INSERT_PHI_TRANS_INSERT]], align 4
+; BE-MEMDEP-NEXT: br label %[[HEADER]]
+; BE-MEMDEP: [[EXIT]]:
+; BE-MEMDEP-NEXT: ret i32 [[L1]]
+;
+; BE-MEMSSA-LABEL: define i32 @phi_trans6(
+; BE-MEMSSA-SAME: ptr noalias readonly captures(none) [[X:%.*]], i1 [[COND:%.*]]) {
+; BE-MEMSSA-NEXT: [[ENTRY:.*]]:
+; BE-MEMSSA-NEXT: [[L0:%.*]] = load i32, ptr [[X]], align 4
+; BE-MEMSSA-NEXT: call void @use_i32(i32 [[L0]])
+; BE-MEMSSA-NEXT: br label %[[HEADER:.*]]
+; BE-MEMSSA: [[HEADER]]:
+; BE-MEMSSA-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
+; BE-MEMSSA-NEXT: indirectbr ptr blockaddress(@phi_trans6, %[[LATCH]]), [label %latch]
+; BE-MEMSSA: [[LATCH]]:
+; BE-MEMSSA-NEXT: [[GEP_1:%.*]] = getelementptr i32, ptr [[X]], i32 [[IV]]
+; BE-MEMSSA-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_1]], align 4
+; BE-MEMSSA-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; BE-MEMSSA-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[HEADER]]
+; BE-MEMSSA: [[EXIT]]:
+; BE-MEMSSA-NEXT: ret i32 [[L1]]
;
entry:
%l0 = load i32, ptr %x
@@ -806,24 +1592,81 @@ exit:
; FIXME: Currently we fail to translate the PHI in this case.
define i32 @phi_trans7(ptr noalias nocapture readonly %x, i1 %cond) {
-; CHECK-LABEL: @phi_trans7(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[L0:%.*]] = load i32, ptr [[X:%.*]], align 4
-; CHECK-NEXT: call void @use_i32(i32 [[L0]])
-; CHECK-NEXT: br label [[HEADER:%.*]]
-; CHECK: header:
-; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 2, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH_HEADER_CRIT_EDGE:%.*]] ]
-; CHECK-NEXT: [[OFFSET:%.*]] = add i32 [[IV]], -2
-; CHECK-NEXT: indirectbr ptr blockaddress(@phi_trans7, [[LATCH:%.*]]), [label %latch]
-; CHECK: latch:
-; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr i32, ptr [[X]], i32 [[OFFSET]]
-; CHECK-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_1]], align 4
-; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
-; CHECK-NEXT: br i1 [[COND:%.*]], label [[EXIT:%.*]], label [[LATCH_HEADER_CRIT_EDGE]]
-; CHECK: latch.header_crit_edge:
-; CHECK-NEXT: br label [[HEADER]]
-; CHECK: exit:
-; CHECK-NEXT: ret i32 [[L1]]
+; LE-MEMDEP-LABEL: define i32 @phi_trans7(
+; LE-MEMDEP-SAME: ptr noalias readonly captures(none) [[X:%.*]], i1 [[COND:%.*]]) {
+; LE-MEMDEP-NEXT: [[ENTRY:.*]]:
+; LE-MEMDEP-NEXT: [[L0:%.*]] = load i32, ptr [[X]], align 4
+; LE-MEMDEP-NEXT: call void @use_i32(i32 [[L0]])
+; LE-MEMDEP-NEXT: br label %[[HEADER:.*]]
+; LE-MEMDEP: [[HEADER]]:
+; LE-MEMDEP-NEXT: [[IV:%.*]] = phi i32 [ 2, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH_HEADER_CRIT_EDGE:.*]] ]
+; LE-MEMDEP-NEXT: [[OFFSET:%.*]] = add i32 [[IV]], -2
+; LE-MEMDEP-NEXT: indirectbr ptr blockaddress(@phi_trans7, %[[LATCH:.*]]), [label %latch]
+; LE-MEMDEP: [[LATCH]]:
+; LE-MEMDEP-NEXT: [[GEP_1:%.*]] = getelementptr i32, ptr [[X]], i32 [[OFFSET]]
+; LE-MEMDEP-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_1]], align 4
+; LE-MEMDEP-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; LE-MEMDEP-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LATCH_HEADER_CRIT_EDGE]]
+; LE-MEMDEP: [[LATCH_HEADER_CRIT_EDGE]]:
+; LE-MEMDEP-NEXT: br label %[[HEADER]]
+; LE-MEMDEP: [[EXIT]]:
+; LE-MEMDEP-NEXT: ret i32 [[L1]]
+;
+; LE-MEMSSA-LABEL: define i32 @phi_trans7(
+; LE-MEMSSA-SAME: ptr noalias readonly captures(none) [[X:%.*]], i1 [[COND:%.*]]) {
+; LE-MEMSSA-NEXT: [[ENTRY:.*]]:
+; LE-MEMSSA-NEXT: [[L0:%.*]] = load i32, ptr [[X]], align 4
+; LE-MEMSSA-NEXT: call void @use_i32(i32 [[L0]])
+; LE-MEMSSA-NEXT: br label %[[HEADER:.*]]
+; LE-MEMSSA: [[HEADER]]:
+; LE-MEMSSA-NEXT: [[IV:%.*]] = phi i32 [ 2, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
+; LE-MEMSSA-NEXT: [[OFFSET:%.*]] = add i32 [[IV]], -2
+; LE-MEMSSA-NEXT: indirectbr ptr blockaddress(@phi_trans7, %[[LATCH]]), [label %latch]
+; LE-MEMSSA: [[LATCH]]:
+; LE-MEMSSA-NEXT: [[GEP_1:%.*]] = getelementptr i32, ptr [[X]], i32 [[OFFSET]]
+; LE-MEMSSA-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_1]], align 4
+; LE-MEMSSA-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; LE-MEMSSA-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[HEADER]]
+; LE-MEMSSA: [[EXIT]]:
+; LE-MEMSSA-NEXT: ret i32 [[L1]]
+;
+; BE-MEMDEP-LABEL: define i32 @phi_trans7(
+; BE-MEMDEP-SAME: ptr noalias readonly captures(none) [[X:%.*]], i1 [[COND:%.*]]) {
+; BE-MEMDEP-NEXT: [[ENTRY:.*]]:
+; BE-MEMDEP-NEXT: [[L0:%.*]] = load i32, ptr [[X]], align 4
+; BE-MEMDEP-NEXT: call void @use_i32(i32 [[L0]])
+; BE-MEMDEP-NEXT: br label %[[HEADER:.*]]
+; BE-MEMDEP: [[HEADER]]:
+; BE-MEMDEP-NEXT: [[IV:%.*]] = phi i32 [ 2, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH_HEADER_CRIT_EDGE:.*]] ]
+; BE-MEMDEP-NEXT: [[OFFSET:%.*]] = add i32 [[IV]], -2
+; BE-MEMDEP-NEXT: indirectbr ptr blockaddress(@phi_trans7, %[[LATCH:.*]]), [label %latch]
+; BE-MEMDEP: [[LATCH]]:
+; BE-MEMDEP-NEXT: [[GEP_1:%.*]] = getelementptr i32, ptr [[X]], i32 [[OFFSET]]
+; BE-MEMDEP-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_1]], align 4
+; BE-MEMDEP-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; BE-MEMDEP-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LATCH_HEADER_CRIT_EDGE]]
+; BE-MEMDEP: [[LATCH_HEADER_CRIT_EDGE]]:
+; BE-MEMDEP-NEXT: br label %[[HEADER]]
+; BE-MEMDEP: [[EXIT]]:
+; BE-MEMDEP-NEXT: ret i32 [[L1]]
+;
+; BE-MEMSSA-LABEL: define i32 @phi_trans7(
+; BE-MEMSSA-SAME: ptr noalias readonly captures(none) [[X:%.*]], i1 [[COND:%.*]]) {
+; BE-MEMSSA-NEXT: [[ENTRY:.*]]:
+; BE-MEMSSA-NEXT: [[L0:%.*]] = load i32, ptr [[X]], align 4
+; BE-MEMSSA-NEXT: call void @use_i32(i32 [[L0]])
+; BE-MEMSSA-NEXT: br label %[[HEADER:.*]]
+; BE-MEMSSA: [[HEADER]]:
+; BE-MEMSSA-NEXT: [[IV:%.*]] = phi i32 [ 2, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
+; BE-MEMSSA-NEXT: [[OFFSET:%.*]] = add i32 [[IV]], -2
+; BE-MEMSSA-NEXT: indirectbr ptr blockaddress(@phi_trans7, %[[LATCH]]), [label %latch]
+; BE-MEMSSA: [[LATCH]]:
+; BE-MEMSSA-NEXT: [[GEP_1:%.*]] = getelementptr i32, ptr [[X]], i32 [[OFFSET]]
+; BE-MEMSSA-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_1]], align 4
+; BE-MEMSSA-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; BE-MEMSSA-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[HEADER]]
+; BE-MEMSSA: [[EXIT]]:
+; BE-MEMSSA-NEXT: ret i32 [[L1]]
;
entry:
%l0 = load i32, ptr %x
@@ -847,24 +1690,81 @@ exit:
; FIXME: Currently we fail to translate the PHI in this case.
define i32 @phi_trans8(ptr noalias nocapture readonly %x, i1 %cond) {
-; CHECK-LABEL: @phi_trans8(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[L0:%.*]] = load i32, ptr [[X:%.*]], align 4
-; CHECK-NEXT: call void @use_i32(i32 [[L0]])
-; CHECK-NEXT: br label [[HEADER:%.*]]
-; CHECK: header:
-; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 2, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH_HEADER_CRIT_EDGE:%.*]] ]
-; CHECK-NEXT: indirectbr ptr blockaddress(@phi_trans8, [[LATCH:%.*]]), [label %latch]
-; CHECK: latch:
-; CHECK-NEXT: [[OFFSET:%.*]] = add i32 [[IV]], -2
-; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr i32, ptr [[X]], i32 [[OFFSET]]
-; CHECK-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_1]], align 4
-; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
-; CHECK-NEXT: br i1 [[COND:%.*]], label [[EXIT:%.*]], label [[LATCH_HEADER_CRIT_EDGE]]
-; CHECK: latch.header_crit_edge:
-; CHECK-NEXT: br label [[HEADER]]
-; CHECK: exit:
-; CHECK-NEXT: ret i32 [[L1]]
+; LE-MEMDEP-LABEL: define i32 @phi_trans8(
+; LE-MEMDEP-SAME: ptr noalias readonly captures(none) [[X:%.*]], i1 [[COND:%.*]]) {
+; LE-MEMDEP-NEXT: [[ENTRY:.*]]:
+; LE-MEMDEP-NEXT: [[L0:%.*]] = load i32, ptr [[X]], align 4
+; LE-MEMDEP-NEXT: call void @use_i32(i32 [[L0]])
+; LE-MEMDEP-NEXT: br label %[[HEADER:.*]]
+; LE-MEMDEP: [[HEADER]]:
+; LE-MEMDEP-NEXT: [[IV:%.*]] = phi i32 [ 2, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH_HEADER_CRIT_EDGE:.*]] ]
+; LE-MEMDEP-NEXT: indirectbr ptr blockaddress(@phi_trans8, %[[LATCH:.*]]), [label %latch]
+; LE-MEMDEP: [[LATCH]]:
+; LE-MEMDEP-NEXT: [[OFFSET:%.*]] = add i32 [[IV]], -2
+; LE-MEMDEP-NEXT: [[GEP_1:%.*]] = getelementptr i32, ptr [[X]], i32 [[OFFSET]]
+; LE-MEMDEP-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_1]], align 4
+; LE-MEMDEP-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; LE-MEMDEP-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LATCH_HEADER_CRIT_EDGE]]
+; LE-MEMDEP: [[LATCH_HEADER_CRIT_EDGE]]:
+; LE-MEMDEP-NEXT: br label %[[HEADER]]
+; LE-MEMDEP: [[EXIT]]:
+; LE-MEMDEP-NEXT: ret i32 [[L1]]
+;
+; LE-MEMSSA-LABEL: define i32 @phi_trans8(
+; LE-MEMSSA-SAME: ptr noalias readonly captures(none) [[X:%.*]], i1 [[COND:%.*]]) {
+; LE-MEMSSA-NEXT: [[ENTRY:.*]]:
+; LE-MEMSSA-NEXT: [[L0:%.*]] = load i32, ptr [[X]], align 4
+; LE-MEMSSA-NEXT: call void @use_i32(i32 [[L0]])
+; LE-MEMSSA-NEXT: br label %[[HEADER:.*]]
+; LE-MEMSSA: [[HEADER]]:
+; LE-MEMSSA-NEXT: [[IV:%.*]] = phi i32 [ 2, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
+; LE-MEMSSA-NEXT: indirectbr ptr blockaddress(@phi_trans8, %[[LATCH]]), [label %latch]
+; LE-MEMSSA: [[LATCH]]:
+; LE-MEMSSA-NEXT: [[OFFSET:%.*]] = add i32 [[IV]], -2
+; LE-MEMSSA-NEXT: [[GEP_1:%.*]] = getelementptr i32, ptr [[X]], i32 [[OFFSET]]
+; LE-MEMSSA-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_1]], align 4
+; LE-MEMSSA-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; LE-MEMSSA-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[HEADER]]
+; LE-MEMSSA: [[EXIT]]:
+; LE-MEMSSA-NEXT: ret i32 [[L1]]
+;
+; BE-MEMDEP-LABEL: define i32 @phi_trans8(
+; BE-MEMDEP-SAME: ptr noalias readonly captures(none) [[X:%.*]], i1 [[COND:%.*]]) {
+; BE-MEMDEP-NEXT: [[ENTRY:.*]]:
+; BE-MEMDEP-NEXT: [[L0:%.*]] = load i32, ptr [[X]], align 4
+; BE-MEMDEP-NEXT: call void @use_i32(i32 [[L0]])
+; BE-MEMDEP-NEXT: br label %[[HEADER:.*]]
+; BE-MEMDEP: [[HEADER]]:
+; BE-MEMDEP-NEXT: [[IV:%.*]] = phi i32 [ 2, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH_HEADER_CRIT_EDGE:.*]] ]
+; BE-MEMDEP-NEXT: indirectbr ptr blockaddress(@phi_trans8, %[[LATCH:.*]]), [label %latch]
+; BE-MEMDEP: [[LATCH]]:
+; BE-MEMDEP-NEXT: [[OFFSET:%.*]] = add i32 [[IV]], -2
+; BE-MEMDEP-NEXT: [[GEP_1:%.*]] = getelementptr i32, ptr [[X]], i32 [[OFFSET]]
+; BE-MEMDEP-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_1]], align 4
+; BE-MEMDEP-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; BE-MEMDEP-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LATCH_HEADER_CRIT_EDGE]]
+; BE-MEMDEP: [[LATCH_HEADER_CRIT_EDGE]]:
+; BE-MEMDEP-NEXT: br label %[[HEADER]]
+; BE-MEMDEP: [[EXIT]]:
+; BE-MEMDEP-NEXT: ret i32 [[L1]]
+;
+; BE-MEMSSA-LABEL: define i32 @phi_trans8(
+; BE-MEMSSA-SAME: ptr noalias readonly captures(none) [[X:%.*]], i1 [[COND:%.*]]) {
+; BE-MEMSSA-NEXT: [[ENTRY:.*]]:
+; BE-MEMSSA-NEXT: [[L0:%.*]] = load i32, ptr [[X]], align 4
+; BE-MEMSSA-NEXT: call void @use_i32(i32 [[L0]])
+; BE-MEMSSA-NEXT: br label %[[HEADER:.*]]
+; BE-MEMSSA: [[HEADER]]:
+; BE-MEMSSA-NEXT: [[IV:%.*]] = phi i32 [ 2, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
+; BE-MEMSSA-NEXT: indirectbr ptr blockaddress(@phi_trans8, %[[LATCH]]), [label %latch]
+; BE-MEMSSA: [[LATCH]]:
+; BE-MEMSSA-NEXT: [[OFFSET:%.*]] = add i32 [[IV]], -2
+; BE-MEMSSA-NEXT: [[GEP_1:%.*]] = getelementptr i32, ptr [[X]], i32 [[OFFSET]]
+; BE-MEMSSA-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_1]], align 4
+; BE-MEMSSA-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; BE-MEMSSA-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[HEADER]]
+; BE-MEMSSA: [[EXIT]]:
+; BE-MEMSSA-NEXT: ret i32 [[L1]]
;
entry:
%l0 = load i32, ptr %x
@@ -890,11 +1790,35 @@ exit:
; PR6642
define i32 @memset_to_load() nounwind readnone {
-; CHECK-LABEL: @memset_to_load(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[X:%.*]] = alloca [256 x i32], align 4
-; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[X]], i8 0, i64 1024, i1 false)
-; CHECK-NEXT: ret i32 0
+; LE-MEMDEP-LABEL: define i32 @memset_to_load(
+; LE-MEMDEP-SAME: ) #[[ATTR2:[0-9]+]] {
+; LE-MEMDEP-NEXT: [[ENTRY:.*:]]
+; LE-MEMDEP-NEXT: [[X:%.*]] = alloca [256 x i32], align 4
+; LE-MEMDEP-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[X]], i8 0, i64 1024, i1 false)
+; LE-MEMDEP-NEXT: ret i32 0
+;
+; LE-MEMSSA-LABEL: define i32 @memset_to_load(
+; LE-MEMSSA-SAME: ) #[[ATTR2:[0-9]+]] {
+; LE-MEMSSA-NEXT: [[ENTRY:.*:]]
+; LE-MEMSSA-NEXT: [[X:%.*]] = alloca [256 x i32], align 4
+; LE-MEMSSA-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[X]], i8 0, i64 1024, i1 false)
+; LE-MEMSSA-NEXT: [[TTMP1:%.*]] = load i32, ptr [[X]], align 4
+; LE-MEMSSA-NEXT: ret i32 [[TTMP1]]
+;
+; BE-MEMDEP-LABEL: define i32 @memset_to_load(
+; BE-MEMDEP-SAME: ) #[[ATTR2:[0-9]+]] {
+; BE-MEMDEP-NEXT: [[ENTRY:.*:]]
+; BE-MEMDEP-NEXT: [[X:%.*]] = alloca [256 x i32], align 4
+; BE-MEMDEP-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[X]], i8 0, i64 1024, i1 false)
+; BE-MEMDEP-NEXT: ret i32 0
+;
+; BE-MEMSSA-LABEL: define i32 @memset_to_load(
+; BE-MEMSSA-SAME: ) #[[ATTR2:[0-9]+]] {
+; BE-MEMSSA-NEXT: [[ENTRY:.*:]]
+; BE-MEMSSA-NEXT: [[X:%.*]] = alloca [256 x i32], align 4
+; BE-MEMSSA-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[X]], i8 0, i64 1024, i1 false)
+; BE-MEMSSA-NEXT: [[TTMP1:%.*]] = load i32, ptr [[X]], align 4
+; BE-MEMSSA-NEXT: ret i32 [[TTMP1]]
;
entry:
%x = alloca [256 x i32], align 4 ; <ptr> [#uses=2]
@@ -910,23 +1834,45 @@ entry:
;;===----------------------------------------------------------------------===;;
define i32 @load_load_partial_alias(ptr %P) nounwind ssp {
-; LE-LABEL: @load_load_partial_alias(
-; LE-NEXT: entry:
-; LE-NEXT: [[TTMP2:%.*]] = load i32, ptr [[P:%.*]], align 4
-; LE-NEXT: [[TMP0:%.*]] = lshr i32 [[TTMP2]], 8
-; LE-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
-; LE-NEXT: [[CONV:%.*]] = zext i8 [[TMP1]] to i32
-; LE-NEXT: [[ADD:%.*]] = add nsw i32 [[TTMP2]], [[CONV]]
-; LE-NEXT: ret i32 [[ADD]]
-;
-; BE-LABEL: @load_load_partial_alias(
-; BE-NEXT: entry:
-; BE-NEXT: [[TTMP2:%.*]] = load i32, ptr [[P:%.*]], align 4
-; BE-NEXT: [[TMP0:%.*]] = lshr i32 [[TTMP2]], 16
-; BE-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
-; BE-NEXT: [[CONV:%.*]] = zext i8 [[TMP1]] to i32
-; BE-NEXT: [[ADD:%.*]] = add nsw i32 [[TTMP2]], [[CONV]]
-; BE-NEXT: ret i32 [[ADD]]
+; LE-MEMDEP-LABEL: define i32 @load_load_partial_alias(
+; LE-MEMDEP-SAME: ptr [[P:%.*]]) #[[ATTR0]] {
+; LE-MEMDEP-NEXT: [[ENTRY:.*:]]
+; LE-MEMDEP-NEXT: [[TTMP2:%.*]] = load i32, ptr [[P]], align 4
+; LE-MEMDEP-NEXT: [[TMP0:%.*]] = lshr i32 [[TTMP2]], 8
+; LE-MEMDEP-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
+; LE-MEMDEP-NEXT: [[CONV:%.*]] = zext i8 [[TMP1]] to i32
+; LE-MEMDEP-NEXT: [[ADD:%.*]] = add nsw i32 [[TTMP2]], [[CONV]]
+; LE-MEMDEP-NEXT: ret i32 [[ADD]]
+;
+; LE-MEMSSA-LABEL: define i32 @load_load_partial_alias(
+; LE-MEMSSA-SAME: ptr [[P:%.*]]) #[[ATTR0]] {
+; LE-MEMSSA-NEXT: [[ENTRY:.*:]]
+; LE-MEMSSA-NEXT: [[TTMP2:%.*]] = load i32, ptr [[P]], align 4
+; LE-MEMSSA-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 1
+; LE-MEMSSA-NEXT: [[TTMP5:%.*]] = load i8, ptr [[ADD_PTR]], align 1
+; LE-MEMSSA-NEXT: [[CONV:%.*]] = zext i8 [[TTMP5]] to i32
+; LE-MEMSSA-NEXT: [[ADD:%.*]] = add nsw i32 [[TTMP2]], [[CONV]]
+; LE-MEMSSA-NEXT: ret i32 [[ADD]]
+;
+; BE-MEMDEP-LABEL: define i32 @load_load_partial_alias(
+; BE-MEMDEP-SAME: ptr [[P:%.*]]) #[[ATTR0]] {
+; BE-MEMDEP-NEXT: [[ENTRY:.*:]]
+; BE-MEMDEP-NEXT: [[TTMP2:%.*]] = load i32, ptr [[P]], align 4
+; BE-MEMDEP-NEXT: [[TMP0:%.*]] = lshr i32 [[TTMP2]], 16
+; BE-MEMDEP-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
+; BE-MEMDEP-NEXT: [[CONV:%.*]] = zext i8 [[TMP1]] to i32
+; BE-MEMDEP-NEXT: [[ADD:%.*]] = add nsw i32 [[TTMP2]], [[CONV]]
+; BE-MEMDEP-NEXT: ret i32 [[ADD]]
+;
+; BE-MEMSSA-LABEL: define i32 @load_load_partial_alias(
+; BE-MEMSSA-SAME: ptr [[P:%.*]]) #[[ATTR0]] {
+; BE-MEMSSA-NEXT: [[ENTRY:.*:]]
+; BE-MEMSSA-NEXT: [[TTMP2:%.*]] = load i32, ptr [[P]], align 4
+; BE-MEMSSA-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 1
+; BE-MEMSSA-NEXT: [[TTMP5:%.*]] = load i8, ptr [[ADD_PTR]], align 1
+; BE-MEMSSA-NEXT: [[CONV:%.*]] = zext i8 [[TTMP5]] to i32
+; BE-MEMSSA-NEXT: [[ADD:%.*]] = add nsw i32 [[TTMP2]], [[CONV]]
+; BE-MEMSSA-NEXT: ret i32 [[ADD]]
;
entry:
%ttmp2 = load i32, ptr %P
@@ -940,31 +1886,61 @@ entry:
; Cross block partial alias case.
define i32 @load_load_partial_alias_cross_block(ptr %P) nounwind ssp {
-; LE-LABEL: @load_load_partial_alias_cross_block(
-; LE-NEXT: entry:
-; LE-NEXT: [[X1:%.*]] = load i32, ptr [[P:%.*]], align 4
-; LE-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
-; LE-NEXT: [[TMP0:%.*]] = lshr i32 [[X1]], 8
-; LE-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
-; LE-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[IF_END:%.*]]
-; LE: land.lhs.true:
-; LE-NEXT: [[CONV6:%.*]] = zext i8 [[TMP1]] to i32
-; LE-NEXT: ret i32 [[CONV6]]
-; LE: if.end:
-; LE-NEXT: ret i32 52
-;
-; BE-LABEL: @load_load_partial_alias_cross_block(
-; BE-NEXT: entry:
-; BE-NEXT: [[X1:%.*]] = load i32, ptr [[P:%.*]], align 4
-; BE-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
-; BE-NEXT: [[TMP0:%.*]] = lshr i32 [[X1]], 16
-; BE-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
-; BE-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[IF_END:%.*]]
-; BE: land.lhs.true:
-; BE-NEXT: [[CONV6:%.*]] = zext i8 [[TMP1]] to i32
-; BE-NEXT: ret i32 [[CONV6]]
-; BE: if.end:
-; BE-NEXT: ret i32 52
+; LE-MEMDEP-LABEL: define i32 @load_load_partial_alias_cross_block(
+; LE-MEMDEP-SAME: ptr [[P:%.*]]) #[[ATTR0]] {
+; LE-MEMDEP-NEXT: [[ENTRY:.*:]]
+; LE-MEMDEP-NEXT: [[X1:%.*]] = load i32, ptr [[P]], align 4
+; LE-MEMDEP-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
+; LE-MEMDEP-NEXT: [[TMP0:%.*]] = lshr i32 [[X1]], 8
+; LE-MEMDEP-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
+; LE-MEMDEP-NEXT: br i1 [[CMP]], label %[[LAND_LHS_TRUE:.*]], label %[[IF_END:.*]]
+; LE-MEMDEP: [[LAND_LHS_TRUE]]:
+; LE-MEMDEP-NEXT: [[CONV6:%.*]] = zext i8 [[TMP1]] to i32
+; LE-MEMDEP-NEXT: ret i32 [[CONV6]]
+; LE-MEMDEP: [[IF_END]]:
+; LE-MEMDEP-NEXT: ret i32 52
+;
+; LE-MEMSSA-LABEL: define i32 @load_load_partial_alias_cross_block(
+; LE-MEMSSA-SAME: ptr [[P:%.*]]) #[[ATTR0]] {
+; LE-MEMSSA-NEXT: [[ENTRY:.*:]]
+; LE-MEMSSA-NEXT: [[X1:%.*]] = load i32, ptr [[P]], align 4
+; LE-MEMSSA-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
+; LE-MEMSSA-NEXT: br i1 [[CMP]], label %[[LAND_LHS_TRUE:.*]], label %[[IF_END:.*]]
+; LE-MEMSSA: [[LAND_LHS_TRUE]]:
+; LE-MEMSSA-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 1
+; LE-MEMSSA-NEXT: [[TTMP5:%.*]] = load i8, ptr [[ARRAYIDX4]], align 1
+; LE-MEMSSA-NEXT: [[CONV6:%.*]] = zext i8 [[TTMP5]] to i32
+; LE-MEMSSA-NEXT: ret i32 [[CONV6]]
+; LE-MEMSSA: [[IF_END]]:
+; LE-MEMSSA-NEXT: ret i32 52
+;
+; BE-MEMDEP-LABEL: define i32 @load_load_partial_alias_cross_block(
+; BE-MEMDEP-SAME: ptr [[P:%.*]]) #[[ATTR0]] {
+; BE-MEMDEP-NEXT: [[ENTRY:.*:]]
+; BE-MEMDEP-NEXT: [[X1:%.*]] = load i32, ptr [[P]], align 4
+; BE-MEMDEP-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
+; BE-MEMDEP-NEXT: [[TMP0:%.*]] = lshr i32 [[X1]], 16
+; BE-MEMDEP-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
+; BE-MEMDEP-NEXT: br i1 [[CMP]], label %[[LAND_LHS_TRUE:.*]], label %[[IF_END:.*]]
+; BE-MEMDEP: [[LAND_LHS_TRUE]]:
+; BE-MEMDEP-NEXT: [[CONV6:%.*]] = zext i8 [[TMP1]] to i32
+; BE-MEMDEP-NEXT: ret i32 [[CONV6]]
+; BE-MEMDEP: [[IF_END]]:
+; BE-MEMDEP-NEXT: ret i32 52
+;
+; BE-MEMSSA-LABEL: define i32 @load_load_partial_alias_cross_block(
+; BE-MEMSSA-SAME: ptr [[P:%.*]]) #[[ATTR0]] {
+; BE-MEMSSA-NEXT: [[ENTRY:.*:]]
+; BE-MEMSSA-NEXT: [[X1:%.*]] = load i32, ptr [[P]], align 4
+; BE-MEMSSA-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
+; BE-MEMSSA-NEXT: br i1 [[CMP]], label %[[LAND_LHS_TRUE:.*]], label %[[IF_END:.*]]
+; BE-MEMSSA: [[LAND_LHS_TRUE]]:
+; BE-MEMSSA-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 1
+; BE-MEMSSA-NEXT: [[TTMP5:%.*]] = load i8, ptr [[ARRAYIDX4]], align 1
+; BE-MEMSSA-NEXT: [[CONV6:%.*]] = zext i8 [[TTMP5]] to i32
+; BE-MEMSSA-NEXT: ret i32 [[CONV6]]
+; BE-MEMSSA: [[IF_END]]:
+; BE-MEMSSA-NEXT: ret i32 52
;
entry:
%x1 = load i32, ptr %P, align 4
@@ -982,45 +1958,85 @@ if.end:
}
define i32 @load_load_partial_alias_cross_block_phi_trans(ptr %P) nounwind {
-; LE-LABEL: @load_load_partial_alias_cross_block_phi_trans(
-; LE-NEXT: entry:
-; LE-NEXT: [[X1:%.*]] = load i32, ptr [[P:%.*]], align 4
-; LE-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
-; LE-NEXT: [[TMP0:%.*]] = lshr i32 [[X1]], 16
-; LE-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
-; LE-NEXT: [[TMP2:%.*]] = lshr i32 [[X1]], 8
-; LE-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
-; LE-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[ELSE:%.*]]
-; LE: if:
-; LE-NEXT: br label [[JOIN:%.*]]
-; LE: else:
-; LE-NEXT: br label [[JOIN]]
-; LE: join:
-; LE-NEXT: [[TTMP5:%.*]] = phi i8 [ [[TMP3]], [[IF]] ], [ [[TMP1]], [[ELSE]] ]
-; LE-NEXT: [[CONV6:%.*]] = zext i8 [[TTMP5]] to i32
-; LE-NEXT: ret i32 [[CONV6]]
-; LE: if.end:
-; LE-NEXT: ret i32 52
-;
-; BE-LABEL: @load_load_partial_alias_cross_block_phi_trans(
-; BE-NEXT: entry:
-; BE-NEXT: [[X1:%.*]] = load i32, ptr [[P:%.*]], align 4
-; BE-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
-; BE-NEXT: [[TMP0:%.*]] = lshr i32 [[X1]], 8
-; BE-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
-; BE-NEXT: [[TMP2:%.*]] = lshr i32 [[X1]], 16
-; BE-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
-; BE-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[ELSE:%.*]]
-; BE: if:
-; BE-NEXT: br label [[JOIN:%.*]]
-; BE: else:
-; BE-NEXT: br label [[JOIN]]
-; BE: join:
-; BE-NEXT: [[TTMP5:%.*]] = phi i8 [ [[TMP3]], [[IF]] ], [ [[TMP1]], [[ELSE]] ]
-; BE-NEXT: [[CONV6:%.*]] = zext i8 [[TTMP5]] to i32
-; BE-NEXT: ret i32 [[CONV6]]
-; BE: if.end:
-; BE-NEXT: ret i32 52
+; LE-MEMDEP-LABEL: define i32 @load_load_partial_alias_cross_block_phi_trans(
+; LE-MEMDEP-SAME: ptr [[P:%.*]]) #[[ATTR3]] {
+; LE-MEMDEP-NEXT: [[ENTRY:.*:]]
+; LE-MEMDEP-NEXT: [[X1:%.*]] = load i32, ptr [[P]], align 4
+; LE-MEMDEP-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
+; LE-MEMDEP-NEXT: [[TMP0:%.*]] = lshr i32 [[X1]], 16
+; LE-MEMDEP-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
+; LE-MEMDEP-NEXT: [[TMP2:%.*]] = lshr i32 [[X1]], 8
+; LE-MEMDEP-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
+; LE-MEMDEP-NEXT: br i1 [[CMP]], label %[[IF:.*]], label %[[ELSE:.*]]
+; LE-MEMDEP: [[IF]]:
+; LE-MEMDEP-NEXT: br label %[[JOIN:.*]]
+; LE-MEMDEP: [[ELSE]]:
+; LE-MEMDEP-NEXT: br label %[[JOIN]]
+; LE-MEMDEP: [[JOIN]]:
+; LE-MEMDEP-NEXT: [[TTMP5:%.*]] = phi i8 [ [[TMP3]], %[[IF]] ], [ [[TMP1]], %[[ELSE]] ]
+; LE-MEMDEP-NEXT: [[CONV6:%.*]] = zext i8 [[TTMP5]] to i32
+; LE-MEMDEP-NEXT: ret i32 [[CONV6]]
+; LE-MEMDEP: [[IF_END:.*:]]
+; LE-MEMDEP-NEXT: ret i32 52
+;
+; LE-MEMSSA-LABEL: define i32 @load_load_partial_alias_cross_block_phi_trans(
+; LE-MEMSSA-SAME: ptr [[P:%.*]]) #[[ATTR3]] {
+; LE-MEMSSA-NEXT: [[ENTRY:.*:]]
+; LE-MEMSSA-NEXT: [[X1:%.*]] = load i32, ptr [[P]], align 4
+; LE-MEMSSA-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
+; LE-MEMSSA-NEXT: br i1 [[CMP]], label %[[IF:.*]], label %[[ELSE:.*]]
+; LE-MEMSSA: [[IF]]:
+; LE-MEMSSA-NEXT: br label %[[JOIN:.*]]
+; LE-MEMSSA: [[ELSE]]:
+; LE-MEMSSA-NEXT: br label %[[JOIN]]
+; LE-MEMSSA: [[JOIN]]:
+; LE-MEMSSA-NEXT: [[IDX:%.*]] = phi i64 [ 1, %[[IF]] ], [ 2, %[[ELSE]] ]
+; LE-MEMSSA-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 [[IDX]]
+; LE-MEMSSA-NEXT: [[TTMP5:%.*]] = load i8, ptr [[ARRAYIDX4]], align 1
+; LE-MEMSSA-NEXT: [[CONV6:%.*]] = zext i8 [[TTMP5]] to i32
+; LE-MEMSSA-NEXT: ret i32 [[CONV6]]
+; LE-MEMSSA: [[IF_END:.*:]]
+; LE-MEMSSA-NEXT: ret i32 52
+;
+; BE-MEMDEP-LABEL: define i32 @load_load_partial_alias_cross_block_phi_trans(
+; BE-MEMDEP-SAME: ptr [[P:%.*]]) #[[ATTR3]] {
+; BE-MEMDEP-NEXT: [[ENTRY:.*:]]
+; BE-MEMDEP-NEXT: [[X1:%.*]] = load i32, ptr [[P]], align 4
+; BE-MEMDEP-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
+; BE-MEMDEP-NEXT: [[TMP0:%.*]] = lshr i32 [[X1]], 8
+; BE-MEMDEP-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
+; BE-MEMDEP-NEXT: [[TMP2:%.*]] = lshr i32 [[X1]], 16
+; BE-MEMDEP-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
+; BE-MEMDEP-NEXT: br i1 [[CMP]], label %[[IF:.*]], label %[[ELSE:.*]]
+; BE-MEMDEP: [[IF]]:
+; BE-MEMDEP-NEXT: br label %[[JOIN:.*]]
+; BE-MEMDEP: [[ELSE]]:
+; BE-MEMDEP-NEXT: br label %[[JOIN]]
+; BE-MEMDEP: [[JOIN]]:
+; BE-MEMDEP-NEXT: [[TTMP5:%.*]] = phi i8 [ [[TMP3]], %[[IF]] ], [ [[TMP1]], %[[ELSE]] ]
+; BE-MEMDEP-NEXT: [[CONV6:%.*]] = zext i8 [[TTMP5]] to i32
+; BE-MEMDEP-NEXT: ret i32 [[CONV6]]
+; BE-MEMDEP: [[IF_END:.*:]]
+; BE-MEMDEP-NEXT: ret i32 52
+;
+; BE-MEMSSA-LABEL: define i32 @load_load_partial_alias_cross_block_phi_trans(
+; BE-MEMSSA-SAME: ptr [[P:%.*]]) #[[ATTR3]] {
+; BE-MEMSSA-NEXT: [[ENTRY:.*:]]
+; BE-MEMSSA-NEXT: [[X1:%.*]] = load i32, ptr [[P]], align 4
+; BE-MEMSSA-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
+; BE-MEMSSA-NEXT: br i1 [[CMP]], label %[[IF:.*]], label %[[ELSE:.*]]
+; BE-MEMSSA: [[IF]]:
+; BE-MEMSSA-NEXT: br label %[[JOIN:.*]]
+; BE-MEMSSA: [[ELSE]]:
+; BE-MEMSSA-NEXT: br label %[[JOIN]]
+; BE-MEMSSA: [[JOIN]]:
+; BE-MEMSSA-NEXT: [[IDX:%.*]] = phi i64 [ 1, %[[IF]] ], [ 2, %[[ELSE]] ]
+; BE-MEMSSA-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 [[IDX]]
+; BE-MEMSSA-NEXT: [[TTMP5:%.*]] = load i8, ptr [[ARRAYIDX4]], align 1
+; BE-MEMSSA-NEXT: [[CONV6:%.*]] = zext i8 [[TTMP5]] to i32
+; BE-MEMSSA-NEXT: ret i32 [[CONV6]]
+; BE-MEMSSA: [[IF_END:.*:]]
+; BE-MEMSSA-NEXT: ret i32 52
;
entry:
%x1 = load i32, ptr %P, align 4
@@ -1047,58 +2063,104 @@ if.end:
}
define void @load_load_partial_alias_loop(ptr %P) {
-; LE-LABEL: @load_load_partial_alias_loop(
-; LE-NEXT: entry:
-; LE-NEXT: [[P_1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1
-; LE-NEXT: [[V_1:%.*]] = load i8, ptr [[P_1]], align 1
-; LE-NEXT: call void @use.i8(i8 [[V_1]])
-; LE-NEXT: [[V_1_32:%.*]] = load i32, ptr [[P_1]], align 4
-; LE-NEXT: call void @use.i32(i32 [[V_1_32]])
-; LE-NEXT: [[TMP0:%.*]] = trunc i32 [[V_1_32]] to i8
-; LE-NEXT: br label [[LOOP:%.*]]
-; LE: loop:
-; LE-NEXT: [[V_I:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[TMP2:%.*]], [[LOOP_LOOP_CRIT_EDGE:%.*]] ]
-; LE-NEXT: [[I:%.*]] = phi i64 [ 1, [[ENTRY]] ], [ [[I_INC:%.*]], [[LOOP_LOOP_CRIT_EDGE]] ]
-; LE-NEXT: [[P_I:%.*]] = getelementptr i8, ptr [[P]], i64 [[I]]
-; LE-NEXT: call void @use.i8(i8 [[V_I]])
-; LE-NEXT: [[V_I_32:%.*]] = load i32, ptr [[P_I]], align 4
-; LE-NEXT: call void @use.i32(i32 [[V_I_32]])
-; LE-NEXT: [[I_INC]] = add i64 [[I]], 1
-; LE-NEXT: [[CMP:%.*]] = icmp ne i64 [[I_INC]], 64
-; LE-NEXT: [[TMP1:%.*]] = lshr i32 [[V_I_32]], 8
-; LE-NEXT: [[TMP2]] = trunc i32 [[TMP1]] to i8
-; LE-NEXT: br i1 [[CMP]], label [[LOOP_LOOP_CRIT_EDGE]], label [[EXIT:%.*]]
-; LE: loop.loop_crit_edge:
-; LE-NEXT: br label [[LOOP]]
-; LE: exit:
-; LE-NEXT: ret void
-;
-; BE-LABEL: @load_load_partial_alias_loop(
-; BE-NEXT: entry:
-; BE-NEXT: [[P_1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1
-; BE-NEXT: [[V_1:%.*]] = load i8, ptr [[P_1]], align 1
-; BE-NEXT: call void @use.i8(i8 [[V_1]])
-; BE-NEXT: [[V_1_32:%.*]] = load i32, ptr [[P_1]], align 4
-; BE-NEXT: call void @use.i32(i32 [[V_1_32]])
-; BE-NEXT: [[TMP0:%.*]] = lshr i32 [[V_1_32]], 24
-; BE-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
-; BE-NEXT: br label [[LOOP:%.*]]
-; BE: loop:
-; BE-NEXT: [[V_I:%.*]] = phi i8 [ [[TMP1]], [[ENTRY:%.*]] ], [ [[TMP3:%.*]], [[LOOP_LOOP_CRIT_EDGE:%.*]] ]
-; BE-NEXT: [[I:%.*]] = phi i64 [ 1, [[ENTRY]] ], [ [[I_INC:%.*]], [[LOOP_LOOP_CRIT_EDGE]] ]
-; BE-NEXT: [[P_I:%.*]] = getelementptr i8, ptr [[P]], i64 [[I]]
-; BE-NEXT: call void @use.i8(i8 [[V_I]])
-; BE-NEXT: [[V_I_32:%.*]] = load i32, ptr [[P_I]], align 4
-; BE-NEXT: call void @use.i32(i32 [[V_I_32]])
-; BE-NEXT: [[I_INC]] = add i64 [[I]], 1
-; BE-NEXT: [[CMP:%.*]] = icmp ne i64 [[I_INC]], 64
-; BE-NEXT: [[TMP2:%.*]] = lshr i32 [[V_I_32]], 16
-; BE-NEXT: [[TMP3]] = trunc i32 [[TMP2]] to i8
-; BE-NEXT: br i1 [[CMP]], label [[LOOP_LOOP_CRIT_EDGE]], label [[EXIT:%.*]]
-; BE: loop.loop_crit_edge:
-; BE-NEXT: br label [[LOOP]]
-; BE: exit:
-; BE-NEXT: ret void
+; LE-MEMDEP-LABEL: define void @load_load_partial_alias_loop(
+; LE-MEMDEP-SAME: ptr [[P:%.*]]) {
+; LE-MEMDEP-NEXT: [[ENTRY:.*]]:
+; LE-MEMDEP-NEXT: [[P_1:%.*]] = getelementptr i8, ptr [[P]], i64 1
+; LE-MEMDEP-NEXT: [[V_1:%.*]] = load i8, ptr [[P_1]], align 1
+; LE-MEMDEP-NEXT: call void @use.i8(i8 [[V_1]])
+; LE-MEMDEP-NEXT: [[V_1_32:%.*]] = load i32, ptr [[P_1]], align 4
+; LE-MEMDEP-NEXT: call void @use.i32(i32 [[V_1_32]])
+; LE-MEMDEP-NEXT: [[TMP0:%.*]] = trunc i32 [[V_1_32]] to i8
+; LE-MEMDEP-NEXT: br label %[[LOOP:.*]]
+; LE-MEMDEP: [[LOOP]]:
+; LE-MEMDEP-NEXT: [[V_I:%.*]] = phi i8 [ [[TMP0]], %[[ENTRY]] ], [ [[TMP2:%.*]], %[[LOOP_LOOP_CRIT_EDGE:.*]] ]
+; LE-MEMDEP-NEXT: [[I:%.*]] = phi i64 [ 1, %[[ENTRY]] ], [ [[I_INC:%.*]], %[[LOOP_LOOP_CRIT_EDGE]] ]
+; LE-MEMDEP-NEXT: [[P_I:%.*]] = getelementptr i8, ptr [[P]], i64 [[I]]
+; LE-MEMDEP-NEXT: call void @use.i8(i8 [[V_I]])
+; LE-MEMDEP-NEXT: [[V_I_32:%.*]] = load i32, ptr [[P_I]], align 4
+; LE-MEMDEP-NEXT: call void @use.i32(i32 [[V_I_32]])
+; LE-MEMDEP-NEXT: [[I_INC]] = add i64 [[I]], 1
+; LE-MEMDEP-NEXT: [[CMP:%.*]] = icmp ne i64 [[I_INC]], 64
+; LE-MEMDEP-NEXT: [[TMP1:%.*]] = lshr i32 [[V_I_32]], 8
+; LE-MEMDEP-NEXT: [[TMP2]] = trunc i32 [[TMP1]] to i8
+; LE-MEMDEP-NEXT: br i1 [[CMP]], label %[[LOOP_LOOP_CRIT_EDGE]], label %[[EXIT:.*]]
+; LE-MEMDEP: [[LOOP_LOOP_CRIT_EDGE]]:
+; LE-MEMDEP-NEXT: br label %[[LOOP]]
+; LE-MEMDEP: [[EXIT]]:
+; LE-MEMDEP-NEXT: ret void
+;
+; LE-MEMSSA-LABEL: define void @load_load_partial_alias_loop(
+; LE-MEMSSA-SAME: ptr [[P:%.*]]) {
+; LE-MEMSSA-NEXT: [[ENTRY:.*]]:
+; LE-MEMSSA-NEXT: [[P_1:%.*]] = getelementptr i8, ptr [[P]], i64 1
+; LE-MEMSSA-NEXT: [[V_1:%.*]] = load i8, ptr [[P_1]], align 1
+; LE-MEMSSA-NEXT: call void @use.i8(i8 [[V_1]])
+; LE-MEMSSA-NEXT: [[V_1_32:%.*]] = load i32, ptr [[P_1]], align 4
+; LE-MEMSSA-NEXT: call void @use.i32(i32 [[V_1_32]])
+; LE-MEMSSA-NEXT: br label %[[LOOP:.*]]
+; LE-MEMSSA: [[LOOP]]:
+; LE-MEMSSA-NEXT: [[I:%.*]] = phi i64 [ 1, %[[ENTRY]] ], [ [[I_INC:%.*]], %[[LOOP]] ]
+; LE-MEMSSA-NEXT: [[P_I:%.*]] = getelementptr i8, ptr [[P]], i64 [[I]]
+; LE-MEMSSA-NEXT: [[V_I:%.*]] = load i8, ptr [[P_I]], align 1
+; LE-MEMSSA-NEXT: call void @use.i8(i8 [[V_I]])
+; LE-MEMSSA-NEXT: [[V_I_32:%.*]] = load i32, ptr [[P_I]], align 4
+; LE-MEMSSA-NEXT: call void @use.i32(i32 [[V_I_32]])
+; LE-MEMSSA-NEXT: [[I_INC]] = add i64 [[I]], 1
+; LE-MEMSSA-NEXT: [[CMP:%.*]] = icmp ne i64 [[I_INC]], 64
+; LE-MEMSSA-NEXT: br i1 [[CMP]], label %[[LOOP]], label %[[EXIT:.*]]
+; LE-MEMSSA: [[EXIT]]:
+; LE-MEMSSA-NEXT: ret void
+;
+; BE-MEMDEP-LABEL: define void @load_load_partial_alias_loop(
+; BE-MEMDEP-SAME: ptr [[P:%.*]]) {
+; BE-MEMDEP-NEXT: [[ENTRY:.*]]:
+; BE-MEMDEP-NEXT: [[P_1:%.*]] = getelementptr i8, ptr [[P]], i64 1
+; BE-MEMDEP-NEXT: [[V_1:%.*]] = load i8, ptr [[P_1]], align 1
+; BE-MEMDEP-NEXT: call void @use.i8(i8 [[V_1]])
+; BE-MEMDEP-NEXT: [[V_1_32:%.*]] = load i32, ptr [[P_1]], align 4
+; BE-MEMDEP-NEXT: call void @use.i32(i32 [[V_1_32]])
+; BE-MEMDEP-NEXT: [[TMP0:%.*]] = lshr i32 [[V_1_32]], 24
+; BE-MEMDEP-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
+; BE-MEMDEP-NEXT: br label %[[LOOP:.*]]
+; BE-MEMDEP: [[LOOP]]:
+; BE-MEMDEP-NEXT: [[V_I:%.*]] = phi i8 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP3:%.*]], %[[LOOP_LOOP_CRIT_EDGE:.*]] ]
+; BE-MEMDEP-NEXT: [[I:%.*]] = phi i64 [ 1, %[[ENTRY]] ], [ [[I_INC:%.*]], %[[LOOP_LOOP_CRIT_EDGE]] ]
+; BE-MEMDEP-NEXT: [[P_I:%.*]] = getelementptr i8, ptr [[P]], i64 [[I]]
+; BE-MEMDEP-NEXT: call void @use.i8(i8 [[V_I]])
+; BE-MEMDEP-NEXT: [[V_I_32:%.*]] = load i32, ptr [[P_I]], align 4
+; BE-MEMDEP-NEXT: call void @use.i32(i32 [[V_I_32]])
+; BE-MEMDEP-NEXT: [[I_INC]] = add i64 [[I]], 1
+; BE-MEMDEP-NEXT: [[CMP:%.*]] = icmp ne i64 [[I_INC]], 64
+; BE-MEMDEP-NEXT: [[TMP2:%.*]] = lshr i32 [[V_I_32]], 16
+; BE-MEMDEP-NEXT: [[TMP3]] = trunc i32 [[TMP2]] to i8
+; BE-MEMDEP-NEXT: br i1 [[CMP]], label %[[LOOP_LOOP_CRIT_EDGE]], label %[[EXIT:.*]]
+; BE-MEMDEP: [[LOOP_LOOP_CRIT_EDGE]]:
+; BE-MEMDEP-NEXT: br label %[[LOOP]]
+; BE-MEMDEP: [[EXIT]]:
+; BE-MEMDEP-NEXT: ret void
+;
+; BE-MEMSSA-LABEL: define void @load_load_partial_alias_loop(
+; BE-MEMSSA-SAME: ptr [[P:%.*]]) {
+; BE-MEMSSA-NEXT: [[ENTRY:.*]]:
+; BE-MEMSSA-NEXT: [[P_1:%.*]] = getelementptr i8, ptr [[P]], i64 1
+; BE-MEMSSA-NEXT: [[V_1:%.*]] = load i8, ptr [[P_1]], align 1
+; BE-MEMSSA-NEXT: call void @use.i8(i8 [[V_1]])
+; BE-MEMSSA-NEXT: [[V_1_32:%.*]] = load i32, ptr [[P_1]], align 4
+; BE-MEMSSA-NEXT: call void @use.i32(i32 [[V_1_32]])
+; BE-MEMSSA-NEXT: br label %[[LOOP:.*]]
+; BE-MEMSSA: [[LOOP]]:
+; BE-MEMSSA-NEXT: [[I:%.*]] = phi i64 [ 1, %[[ENTRY]] ], [ [[I_INC:%.*]], %[[LOOP]] ]
+; BE-MEMSSA-NEXT: [[P_I:%.*]] = getelementptr i8, ptr [[P]], i64 [[I]]
+; BE-MEMSSA-NEXT: [[V_I:%.*]] = load i8, ptr [[P_I]], align 1
+; BE-MEMSSA-NEXT: call void @use.i8(i8 [[V_I]])
+; BE-MEMSSA-NEXT: [[V_I_32:%.*]] = load i32, ptr [[P_I]], align 4
+; BE-MEMSSA-NEXT: call void @use.i32(i32 [[V_I_32]])
+; BE-MEMSSA-NEXT: [[I_INC]] = add i64 [[I]], 1
+; BE-MEMSSA-NEXT: [[CMP:%.*]] = icmp ne i64 [[I_INC]], 64
+; BE-MEMSSA-NEXT: br i1 [[CMP]], label %[[LOOP]], label %[[EXIT:.*]]
+; BE-MEMSSA: [[EXIT]]:
+; BE-MEMSSA-NEXT: ret void
;
entry:
%P.1 = getelementptr i8, ptr %P, i64 1
@@ -1129,37 +2191,63 @@ declare void @use.i32(i32) readnone
@global = external local_unnamed_addr global i8, align 4
define void @load_load_partial_alias_atomic(ptr %arg) {
-; LE-LABEL: @load_load_partial_alias_atomic(
-; LE-NEXT: bb:
-; LE-NEXT: [[TMP2_1:%.*]] = getelementptr inbounds i8, ptr [[ARG:%.*]], i64 1
-; LE-NEXT: [[TMP2_3:%.*]] = load i64, ptr [[TMP2_1]], align 4
-; LE-NEXT: [[TMP3_1:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 2
-; LE-NEXT: [[TMP0:%.*]] = lshr i64 [[TMP2_3]], 8
-; LE-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i8
-; LE-NEXT: br label [[BB5:%.*]]
-; LE: bb5:
-; LE-NEXT: [[TMP4_1:%.*]] = phi i8 [ [[TMP4_1_PRE:%.*]], [[BB5]] ], [ [[TMP1]], [[BB:%.*]] ]
-; LE-NEXT: [[TMP6_1:%.*]] = load atomic i8, ptr @global acquire, align 4
-; LE-NEXT: [[TMP7_1:%.*]] = add i8 [[TMP6_1]], [[TMP4_1]]
-; LE-NEXT: store i8 [[TMP7_1]], ptr [[ARG]], align 1
-; LE-NEXT: [[TMP4_1_PRE]] = load i8, ptr [[TMP3_1]], align 4
-; LE-NEXT: br label [[BB5]]
-;
-; BE-LABEL: @load_load_partial_alias_atomic(
-; BE-NEXT: bb:
-; BE-NEXT: [[TMP2_1:%.*]] = getelementptr inbounds i8, ptr [[ARG:%.*]], i64 1
-; BE-NEXT: [[TMP2_3:%.*]] = load i64, ptr [[TMP2_1]], align 4
-; BE-NEXT: [[TMP3_1:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 2
-; BE-NEXT: [[TMP0:%.*]] = lshr i64 [[TMP2_3]], 48
-; BE-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i8
-; BE-NEXT: br label [[BB5:%.*]]
-; BE: bb5:
-; BE-NEXT: [[TMP4_1:%.*]] = phi i8 [ [[TMP4_1_PRE:%.*]], [[BB5]] ], [ [[TMP1]], [[BB:%.*]] ]
-; BE-NEXT: [[TMP6_1:%.*]] = load atomic i8, ptr @global acquire, align 4
-; BE-NEXT: [[TMP7_1:%.*]] = add i8 [[TMP6_1]], [[TMP4_1]]
-; BE-NEXT: store i8 [[TMP7_1]], ptr [[ARG]], align 1
-; BE-NEXT: [[TMP4_1_PRE]] = load i8, ptr [[TMP3_1]], align 4
-; BE-NEXT: br label [[BB5]]
+; LE-MEMDEP-LABEL: define void @load_load_partial_alias_atomic(
+; LE-MEMDEP-SAME: ptr [[ARG:%.*]]) {
+; LE-MEMDEP-NEXT: [[BB:.*]]:
+; LE-MEMDEP-NEXT: [[TMP2_1:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 1
+; LE-MEMDEP-NEXT: [[TMP2_3:%.*]] = load i64, ptr [[TMP2_1]], align 4
+; LE-MEMDEP-NEXT: [[TMP3_1:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 2
+; LE-MEMDEP-NEXT: [[TMP0:%.*]] = lshr i64 [[TMP2_3]], 8
+; LE-MEMDEP-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i8
+; LE-MEMDEP-NEXT: br label %[[BB5:.*]]
+; LE-MEMDEP: [[BB5]]:
+; LE-MEMDEP-NEXT: [[TMP4_1:%.*]] = phi i8 [ [[TMP4_1_PRE:%.*]], %[[BB5]] ], [ [[TMP1]], %[[BB]] ]
+; LE-MEMDEP-NEXT: [[TMP6_1:%.*]] = load atomic i8, ptr @global acquire, align 4
+; LE-MEMDEP-NEXT: [[TMP7_1:%.*]] = add i8 [[TMP6_1]], [[TMP4_1]]
+; LE-MEMDEP-NEXT: store i8 [[TMP7_1]], ptr [[ARG]], align 1
+; LE-MEMDEP-NEXT: [[TMP4_1_PRE]] = load i8, ptr [[TMP3_1]], align 4
+; LE-MEMDEP-NEXT: br label %[[BB5]]
+;
+; LE-MEMSSA-LABEL: define void @load_load_partial_alias_atomic(
+; LE-MEMSSA-SAME: ptr [[ARG:%.*]]) {
+; LE-MEMSSA-NEXT: [[BB:.*:]]
+; LE-MEMSSA-NEXT: [[TMP3_1:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 2
+; LE-MEMSSA-NEXT: br label %[[BB5:.*]]
+; LE-MEMSSA: [[BB5]]:
+; LE-MEMSSA-NEXT: [[TMP4_1:%.*]] = load i8, ptr [[TMP3_1]], align 4
+; LE-MEMSSA-NEXT: [[TMP6_1:%.*]] = load atomic i8, ptr @global acquire, align 4
+; LE-MEMSSA-NEXT: [[TMP7_1:%.*]] = add i8 [[TMP6_1]], [[TMP4_1]]
+; LE-MEMSSA-NEXT: store i8 [[TMP7_1]], ptr [[ARG]], align 1
+; LE-MEMSSA-NEXT: br label %[[BB5]]
+;
+; BE-MEMDEP-LABEL: define void @load_load_partial_alias_atomic(
+; BE-MEMDEP-SAME: ptr [[ARG:%.*]]) {
+; BE-MEMDEP-NEXT: [[BB:.*]]:
+; BE-MEMDEP-NEXT: [[TMP2_1:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 1
+; BE-MEMDEP-NEXT: [[TMP2_3:%.*]] = load i64, ptr [[TMP2_1]], align 4
+; BE-MEMDEP-NEXT: [[TMP3_1:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 2
+; BE-MEMDEP-NEXT: [[TMP0:%.*]] = lshr i64 [[TMP2_3]], 48
+; BE-MEMDEP-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i8
+; BE-MEMDEP-NEXT: br label %[[BB5:.*]]
+; BE-MEMDEP: [[BB5]]:
+; BE-MEMDEP-NEXT: [[TMP4_1:%.*]] = phi i8 [ [[TMP4_1_PRE:%.*]], %[[BB5]] ], [ [[TMP1]], %[[BB]] ]
+; BE-MEMDEP-NEXT: [[TMP6_1:%.*]] = load atomic i8, ptr @global acquire, align 4
+; BE-MEMDEP-NEXT: [[TMP7_1:%.*]] = add i8 [[TMP6_1]], [[TMP4_1]]
+; BE-MEMDEP-NEXT: store i8 [[TMP7_1]], ptr [[ARG]], align 1
+; BE-MEMDEP-NEXT: [[TMP4_1_PRE]] = load i8, ptr [[TMP3_1]], align 4
+; BE-MEMDEP-NEXT: br label %[[BB5]]
+;
+; BE-MEMSSA-LABEL: define void @load_load_partial_alias_atomic(
+; BE-MEMSSA-SAME: ptr [[ARG:%.*]]) {
+; BE-MEMSSA-NEXT: [[BB:.*:]]
+; BE-MEMSSA-NEXT: [[TMP3_1:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 2
+; BE-MEMSSA-NEXT: br label %[[BB5:.*]]
+; BE-MEMSSA: [[BB5]]:
+; BE-MEMSSA-NEXT: [[TMP4_1:%.*]] = load i8, ptr [[TMP3_1]], align 4
+; BE-MEMSSA-NEXT: [[TMP6_1:%.*]] = load atomic i8, ptr @global acquire, align 4
+; BE-MEMSSA-NEXT: [[TMP7_1:%.*]] = add i8 [[TMP6_1]], [[TMP4_1]]
+; BE-MEMSSA-NEXT: store i8 [[TMP7_1]], ptr [[ARG]], align 1
+; BE-MEMSSA-NEXT: br label %[[BB5]]
;
bb:
%tmp2.1 = getelementptr inbounds i8, ptr %arg, i64 1
@@ -1188,8 +2276,9 @@ bb5: ; preds = %bb14, %bb
@f = global %widening1 zeroinitializer, align 4
define i32 @test_widening1(ptr %P) nounwind ssp noredzone {
-; CHECK-LABEL: @test_widening1(
-; CHECK-NEXT: entry:
+; CHECK-LABEL: define i32 @test_widening1(
+; CHECK-SAME: ptr [[P:%.*]]) #[[ATTR5:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TTMP:%.*]] = load i8, ptr getelementptr inbounds ([[WIDENING1:%.*]], ptr @f, i64 0, i32 1), align 4
; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TTMP]] to i32
; CHECK-NEXT: [[TTMP1:%.*]] = load i8, ptr getelementptr inbounds ([[WIDENING1]], ptr @f, i64 0, i32 2), align 1
@@ -1207,8 +2296,9 @@ entry:
}
define i32 @test_widening2() nounwind ssp noredzone {
-; CHECK-LABEL: @test_widening2(
-; CHECK-NEXT: entry:
+; CHECK-LABEL: define i32 @test_widening2(
+; CHECK-SAME: ) #[[ATTR5]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TTMP:%.*]] = load i8, ptr getelementptr inbounds ([[WIDENING1:%.*]], ptr @f, i64 0, i32 1), align 4
; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TTMP]] to i32
; CHECK-NEXT: [[TTMP1:%.*]] = load i8, ptr getelementptr inbounds ([[WIDENING1]], ptr @f, i64 0, i32 2), align 1
@@ -1262,12 +2352,39 @@ declare void @use3(ptr, ptr)
; PR8908
define void @test_escape1() nounwind {
-; CHECK-LABEL: @test_escape1(
-; CHECK-NEXT: [[X:%.*]] = alloca ptr, align 8
-; CHECK-NEXT: store ptr getelementptr inbounds ([5 x ptr], ptr @_ZTV1X, i64 0, i64 2), ptr [[X]], align 8
-; CHECK-NEXT: call void @use() #[[ATTR3]]
-; CHECK-NEXT: call void @use3(ptr [[X]], ptr getelementptr inbounds ([5 x ptr], ptr @_ZTV1X, i64 0, i64 2)) #[[ATTR3]]
-; CHECK-NEXT: ret void
+; LE-MEMDEP-LABEL: define void @test_escape1(
+; LE-MEMDEP-SAME: ) #[[ATTR3]] {
+; LE-MEMDEP-NEXT: [[X:%.*]] = alloca ptr, align 8
+; LE-MEMDEP-NEXT: store ptr getelementptr inbounds ([5 x ptr], ptr @_ZTV1X, i64 0, i64 2), ptr [[X]], align 8
+; LE-MEMDEP-NEXT: call void @use() #[[ATTR3]]
+; LE-MEMDEP-NEXT: call void @use3(ptr [[X]], ptr getelementptr inbounds ([5 x ptr], ptr @_ZTV1X, i64 0, i64 2)) #[[ATTR3]]
+; LE-MEMDEP-NEXT: ret void
+;
+; LE-MEMSSA-LABEL: define void @test_escape1(
+; LE-MEMSSA-SAME: ) #[[ATTR3]] {
+; LE-MEMSSA-NEXT: [[X:%.*]] = alloca ptr, align 8
+; LE-MEMSSA-NEXT: store ptr getelementptr inbounds ([5 x ptr], ptr @_ZTV1X, i64 0, i64 2), ptr [[X]], align 8
+; LE-MEMSSA-NEXT: call void @use() #[[ATTR3]]
+; LE-MEMSSA-NEXT: [[DEAD:%.*]] = load ptr, ptr [[X]], align 8
+; LE-MEMSSA-NEXT: call void @use3(ptr [[X]], ptr [[DEAD]]) #[[ATTR3]]
+; LE-MEMSSA-NEXT: ret void
+;
+; BE-MEMDEP-LABEL: define void @test_escape1(
+; BE-MEMDEP-SAME: ) #[[ATTR3]] {
+; BE-MEMDEP-NEXT: [[X:%.*]] = alloca ptr, align 8
+; BE-MEMDEP-NEXT: store ptr getelementptr inbounds ([5 x ptr], ptr @_ZTV1X, i64 0, i64 2), ptr [[X]], align 8
+; BE-MEMDEP-NEXT: call void @use() #[[ATTR3]]
+; BE-MEMDEP-NEXT: call void @use3(ptr [[X]], ptr getelementptr inbounds ([5 x ptr], ptr @_ZTV1X, i64 0, i64 2)) #[[ATTR3]]
+; BE-MEMDEP-NEXT: ret void
+;
+; BE-MEMSSA-LABEL: define void @test_escape1(
+; BE-MEMSSA-SAME: ) #[[ATTR3]] {
+; BE-MEMSSA-NEXT: [[X:%.*]] = alloca ptr, align 8
+; BE-MEMSSA-NEXT: store ptr getelementptr inbounds ([5 x ptr], ptr @_ZTV1X, i64 0, i64 2), ptr [[X]], align 8
+; BE-MEMSSA-NEXT: call void @use() #[[ATTR3]]
+; BE-MEMSSA-NEXT: [[DEAD:%.*]] = load ptr, ptr [[X]], align 8
+; BE-MEMSSA-NEXT: call void @use3(ptr [[X]], ptr [[DEAD]]) #[[ATTR3]]
+; BE-MEMSSA-NEXT: ret void
;
%x = alloca ptr, align 8
store ptr getelementptr inbounds ([5 x ptr], ptr @_ZTV1X, i64 0, i64 2), ptr %x, align 8
@@ -1276,3 +2393,6 @@ define void @test_escape1() nounwind {
call void @use3(ptr %x, ptr %DEAD) nounwind
ret void
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; BE: {{.*}}
+; LE: {{.*}}
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