[llvm] [RISCV] Implement EmitTargetCodeForMemset for Xqcilsm (PR #151555)

[Sudharsan Veeravalli via llvm-commits]

================
@@ -1845,6 +1845,15 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     CurDAG->RemoveDeadNode(Node);
     return;
   }
+  case RISCVISD::QC_SETWMI: {
+    SDValue Chain = Node->getOperand(0);
+    SDVTList VTs = Node->getVTList();
+    SDValue Ops[] = {Node->getOperand(1), Node->getOperand(2),
+                     Node->getOperand(3), Node->getOperand(4), Chain};
+    MachineSDNode *New = CurDAG->getMachineNode(RISCV::QC_SETWMI, DL, VTs, Ops);
+    ReplaceNode(Node, New);
----------------
svs-quic wrote:

Thanks. I remember I had looked at this but had run into issues due to the way I had written the pattern. 
For now, I've copied over the memoperand in the Select() function.

When I write a pattern like this:

```
let Predicates = [HasVendorXqcilsm, IsRV32] in {
def : Pat<(qc_setwmi i32:$rd, GPR:$rs1, uimm5nonzero:$uimm5, uimm7_lsb00:$uimm7),
          (QC_SETWMI i32:$rd, GPR:$rs1, uimm5nonzero:$uimm5, uimm7_lsb00:$uimm7)>;
} // Predicates = [HasVendorXqcilsm, IsRV32]
 
```
 
 I'm running into the following selection error:
 ```

 ISEL: Starting selection on root node: t10: ch = RISCVISD::QC_SETWMI<(store (s512) into %ir.p, align 4)> t0, Constant:i32<-1515870811>, t2, TargetConstant:i32<16>, TargetConstant:i32<64>
ISEL: Starting pattern match
  Initial Opcode index to 1260245
  Match failed at index 1260253
LLVM ERROR: Cannot select: t10: ch = RISCVISD::QC_SETWMI<(store (s512) into %ir.p, align 4)> t0, Constant:i32<-1515870811>, t2, TargetConstant:i32<16>, TargetConstant:i32<64>
```

Obviously, I'm missing something here. 


https://github.com/llvm/llvm-project/pull/151555