[llvm] [Intrinsics][AArch64] Add intrinsic to mask off aliasing vector lanes (PR #117007)

[Sander de Smalen via llvm-commits]

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@@ -1899,6 +1899,16 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
     }
   }
 
+  // Handle non-aliasing elements mask
+  if (Subtarget->hasSVE2() ||
+      (Subtarget->hasSME() && Subtarget->isStreaming())) {
+    for (auto VT : {MVT::v2i32, MVT::v4i16, MVT::v8i8, MVT::v16i8, MVT::nxv2i1,
+                    MVT::nxv4i1, MVT::nxv8i1, MVT::nxv16i1}) {
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sdesmalen-arm wrote:

Please split this into two loops, one for scalable vectors (where the operation action should be `Legal`) and one for the fixed-length types (using `Custom`). Also add a FIXME that we need to support wider fixed-length types for when `msve-vector-bits` is used.

https://github.com/llvm/llvm-project/pull/117007