[llvm] [AMDGPU] Check noalias.addrspace in mayAccessScratchThroughFlat (PR #151319)
Pierre van Houtryve via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 1 03:03:21 PDT 2025
https://github.com/Pierre-vh updated https://github.com/llvm/llvm-project/pull/151319
>From dd7ca13970e980fa7464cfdc1fa8e2753b81476a Mon Sep 17 00:00:00 2001
From: pvanhout <pierre.vanhoutryve at amd.com>
Date: Wed, 30 Jul 2025 14:18:46 +0200
Subject: [PATCH 1/2] [AMDGPU] Check noalias.addrspace in
mayAccessScratchThroughFlat
PR #149247 made the MD accessible by the backend so we can now leverage it
in the memory model. The first use case here is detecting if a flat op
can access scratch memory.
Benefits both the MemoryLegalizer and InsertWaitCnt.
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 22 ++++++++++++++++++-
.../AMDGPU/gfx1250-scratch-scope-se.ll | 5 ++---
2 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index c2da937552240..509bb2cb1428c 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4249,6 +4249,24 @@ bool SIInstrInfo::isAlwaysGDS(uint16_t Opcode) const {
Opcode == AMDGPU::DS_SUB_GS_REG_RTN || isGWS(Opcode);
}
+static bool hasNoAliasAddrSpaceScratch(const MachineMemOperand *MemOp) {
+ const MDNode *MD = MemOp->getAAInfo().NoAliasAddrSpace;
+ if (!MD)
+ return false;
+
+ // This MD is structured in ranges [A, B)
+ // Check if PRIVATE is included in any of them.
+ for (unsigned I = 0, E = MD->getNumOperands() / 2; I != E; ++I) {
+ auto *Low = mdconst::extract<ConstantInt>(MD->getOperand(2 * I + 0));
+ auto *High = mdconst::extract<ConstantInt>(MD->getOperand(2 * I + 1));
+ if (Low->getValue().ule(AMDGPUAS::PRIVATE_ADDRESS) &&
+ High->getValue().ugt(AMDGPUAS::PRIVATE_ADDRESS))
+ return true;
+ }
+
+ return false;
+}
+
bool SIInstrInfo::mayAccessScratchThroughFlat(const MachineInstr &MI) const {
if (!isFLAT(MI) || isFLATGlobal(MI))
return false;
@@ -4271,7 +4289,9 @@ bool SIInstrInfo::mayAccessScratchThroughFlat(const MachineInstr &MI) const {
// See if any memory operand specifies an address space that involves scratch.
return any_of(MI.memoperands(), [](const MachineMemOperand *Memop) {
unsigned AS = Memop->getAddrSpace();
- return AS == AMDGPUAS::PRIVATE_ADDRESS || AS == AMDGPUAS::FLAT_ADDRESS;
+ if (AS == AMDGPUAS::FLAT_ADDRESS)
+ return !hasNoAliasAddrSpaceScratch(Memop);
+ return AS == AMDGPUAS::PRIVATE_ADDRESS;
});
}
diff --git a/llvm/test/CodeGen/AMDGPU/gfx1250-scratch-scope-se.ll b/llvm/test/CodeGen/AMDGPU/gfx1250-scratch-scope-se.ll
index d1e82a06077f5..99025f0a983c0 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx1250-scratch-scope-se.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx1250-scratch-scope-se.ll
@@ -39,20 +39,19 @@ define void @test_flat_store_no_scratch_alloc(ptr %ptr, i32 %val) #0 {
ret void
}
-; TODO: handle
define void @test_flat_store_noalias_addrspace(ptr %ptr, i32 %val) {
; GCN-LABEL: test_flat_store_noalias_addrspace:
; GCN: ; %bb.0:
; GCN-NEXT: s_wait_loadcnt_dscnt 0x0
; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GCN-NEXT: flat_store_b32 v[0:1], v2
; GCN-NEXT: s_wait_dscnt 0x0
; GCN-NEXT: s_set_pc_i64 s[30:31]
store i32 %val, ptr %ptr, !noalias.addrspace !{i32 5, i32 6}
ret void
}
-; TODO: would be nice to handle too
+; TODO: would be nice to handle
define void @test_flat_store_select(ptr addrspace(1) %a, ptr addrspace(3) %b, i1 %cond, i32 %val) {
; GCN-SDAG-LABEL: test_flat_store_select:
; GCN-SDAG: ; %bb.0:
>From 239b9c04d077745a5f96ae57c018c3bf3981d02c Mon Sep 17 00:00:00 2001
From: pvanhout <pierre.vanhoutryve at amd.com>
Date: Fri, 1 Aug 2025 12:03:07 +0200
Subject: [PATCH 2/2] Use shared helper
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 17 ++------------
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 23 ++-----------------
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 17 ++++++++++++++
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 5 ++++
4 files changed, 26 insertions(+), 36 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 579ca96a76200..cce6d656ca719 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -17655,21 +17655,8 @@ atomicSupportedIfLegalIntType(const AtomicRMWInst *RMW) {
static bool flatInstrMayAccessPrivate(const Instruction *I) {
const MDNode *NoaliasAddrSpaceMD =
I->getMetadata(LLVMContext::MD_noalias_addrspace);
- if (!NoaliasAddrSpaceMD)
- return true;
-
- for (unsigned I = 0, E = NoaliasAddrSpaceMD->getNumOperands() / 2; I != E;
- ++I) {
- auto *Low = mdconst::extract<ConstantInt>(
- NoaliasAddrSpaceMD->getOperand(2 * I + 0));
- if (Low->getValue().uge(AMDGPUAS::PRIVATE_ADDRESS)) {
- auto *High = mdconst::extract<ConstantInt>(
- NoaliasAddrSpaceMD->getOperand(2 * I + 1));
- return High->getValue().ule(AMDGPUAS::PRIVATE_ADDRESS);
- }
- }
-
- return true;
+ return !AMDGPU::hasValueInRange(NoaliasAddrSpaceMD,
+ AMDGPUAS::PRIVATE_ADDRESS);
}
TargetLowering::AtomicExpansionKind
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 509bb2cb1428c..614dfa346a1f5 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4249,24 +4249,6 @@ bool SIInstrInfo::isAlwaysGDS(uint16_t Opcode) const {
Opcode == AMDGPU::DS_SUB_GS_REG_RTN || isGWS(Opcode);
}
-static bool hasNoAliasAddrSpaceScratch(const MachineMemOperand *MemOp) {
- const MDNode *MD = MemOp->getAAInfo().NoAliasAddrSpace;
- if (!MD)
- return false;
-
- // This MD is structured in ranges [A, B)
- // Check if PRIVATE is included in any of them.
- for (unsigned I = 0, E = MD->getNumOperands() / 2; I != E; ++I) {
- auto *Low = mdconst::extract<ConstantInt>(MD->getOperand(2 * I + 0));
- auto *High = mdconst::extract<ConstantInt>(MD->getOperand(2 * I + 1));
- if (Low->getValue().ule(AMDGPUAS::PRIVATE_ADDRESS) &&
- High->getValue().ugt(AMDGPUAS::PRIVATE_ADDRESS))
- return true;
- }
-
- return false;
-}
-
bool SIInstrInfo::mayAccessScratchThroughFlat(const MachineInstr &MI) const {
if (!isFLAT(MI) || isFLATGlobal(MI))
return false;
@@ -4284,13 +4266,12 @@ bool SIInstrInfo::mayAccessScratchThroughFlat(const MachineInstr &MI) const {
if (MI.memoperands_empty())
return true;
- // TODO (?): Does this need to be taught how to read noalias.addrspace ?
-
// See if any memory operand specifies an address space that involves scratch.
return any_of(MI.memoperands(), [](const MachineMemOperand *Memop) {
unsigned AS = Memop->getAddrSpace();
if (AS == AMDGPUAS::FLAT_ADDRESS)
- return !hasNoAliasAddrSpaceScratch(Memop);
+ return !AMDGPU::hasValueInRange(Memop->getAAInfo().NoAliasAddrSpace,
+ AMDGPUAS::PRIVATE_ADDRESS);
return AS == AMDGPUAS::PRIVATE_ADDRESS;
});
}
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 83e63ac4e9777..2bf24a992a5f9 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -21,6 +21,7 @@
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/IR/IntrinsicsR600.h"
#include "llvm/IR/LLVMContext.h"
+#include "llvm/IR/Metadata.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
@@ -1630,6 +1631,22 @@ getIntegerVecAttribute(const Function &F, StringRef Name, unsigned Size) {
return Vals;
}
+bool hasValueInRange(const MDNode *MD, unsigned Val) {
+ if (!MD)
+ return false;
+
+ assert((MD->getNumOperands() % 2 == 0) && "invalid number of operands!");
+ for (unsigned I = 0, E = MD->getNumOperands() / 2; I != E; ++I) {
+ auto *Low = mdconst::extract<ConstantInt>(MD->getOperand(2 * I + 0));
+ auto *High = mdconst::extract<ConstantInt>(MD->getOperand(2 * I + 1));
+ assert(Low->getValue().ult(High->getValue()) && "invalid range metadata!");
+ if (Low->getValue().ule(Val) && High->getValue().ugt(Val))
+ return true;
+ }
+
+ return false;
+}
+
unsigned getVmcntBitMask(const IsaVersion &Version) {
return (1 << (getVmcntBitWidthLo(Version.Major) +
getVmcntBitWidthHi(Version.Major))) -
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index c09a9d694f3d8..05cb7c9f0d710 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -35,6 +35,7 @@ class MCInstrInfo;
class MCRegisterClass;
class MCRegisterInfo;
class MCSubtargetInfo;
+class MDNode;
class StringRef;
class Triple;
class raw_ostream;
@@ -1058,6 +1059,10 @@ SmallVector<unsigned> getIntegerVecAttribute(const Function &F, StringRef Name,
std::optional<SmallVector<unsigned>>
getIntegerVecAttribute(const Function &F, StringRef Name, unsigned Size);
+/// Checks if \p Val is inside \p MD, a !range-like metadata.
+/// Returns false if \p MD is null.
+bool hasValueInRange(const MDNode *MD, unsigned Val);
+
/// Represents the counter values to wait for in an s_waitcnt instruction.
///
/// Large values (including the maximum possible integer) can be used to
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