[llvm] [AMDGPU][GlobalISel] Add combines with or/and that only use half of 64bit values (PR #151519)

[Matt Arsenault via llvm-commits]

================
@@ -151,6 +151,21 @@ def zext_of_shift_amount_combines : GICombineGroup<[
   canonicalize_zext_lshr, canonicalize_zext_ashr, canonicalize_zext_shl
 ]>;
 
+// (or i64:x, (zext i32:y)) -> i64:(merge (or i32:y, lo_32(x)), hi_32(x))
+def combine_or_s64_s32 : GICombineRule<
+  (defs root:$dst),
+  (match (G_ZEXT $zext_val, i32:$src_s32):$zext_inst,
+         (G_OR $dst, i64:$src_s64, $zext_val):$dst),
+  (apply [{ Helper.applyCombineOrS64S32(*${dst}, ${src_s64}.getReg(), ${src_s32}.getReg()); }])>;
+
+// (and i64:x, 0xFFFFFFFF00000000) -> i64:(merge i32:0, hi_32(x))
----------------
arsenm wrote:

This is essentially a port of splitBinaryBitConstantOp, which has more conditions on the constant 

https://github.com/llvm/llvm-project/pull/151519