[llvm] [RISCV] Implement EmitTargetCodeForMemset for Xqcilsm (PR #151555)

[Craig Topper via llvm-commits]

================
@@ -1845,6 +1845,15 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     CurDAG->RemoveDeadNode(Node);
     return;
   }
+  case RISCVISD::QC_SETWMI: {
+    SDValue Chain = Node->getOperand(0);
+    SDVTList VTs = Node->getVTList();
+    SDValue Ops[] = {Node->getOperand(1), Node->getOperand(2),
+                     Node->getOperand(3), Node->getOperand(4), Chain};
+    MachineSDNode *New = CurDAG->getMachineNode(RISCV::QC_SETWMI, DL, VTs, Ops);
+    ReplaceNode(Node, New);
----------------
topperc wrote:

> I'm figuring this out. Just copying the memoperand here leads to a crash.
> 
> > But its not clear to me why we can't use isel pattern for this which would handle that using SDNPMemOperand
> 
> Is there an example of something similar for a `RISCVISD::` node?

```
let Predicates = [HasVendorXTHeadMemPair, IsRV64] in {                           
def : Pat<(th_lwud i64:$rs1, uimm2_3:$uimm2_3), (TH_LWUD i64:$rs1, uimm2_3:$uimm2_3, 3)>;
def : Pat<(th_ldd i64:$rs1, uimm2_4:$uimm2_4), (TH_LDD i64:$rs1, uimm2_4:$uimm2_4, 4)>;
                                                                                 
def : Pat<(th_sdd i64:$rd1, i64:$rd2, i64:$rs1, uimm2_4:$uimm2_4),               
          (TH_SDD i64:$rd1, i64:$rd2, i64:$rs1, uimm2_4:$uimm2_4, 4)>;           
}   
```

https://github.com/llvm/llvm-project/pull/151555