[llvm] [RISCV] Implement EmitTargetCodeForMemset for Xqcilsm (PR #151555)

[Sam Elliott via llvm-commits]

================
@@ -62,3 +64,102 @@ void RISCVSelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG,
   }
 #endif
 }
+
+SDValue RISCVSelectionDAGInfo::EmitTargetCodeForMemset(
+    SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
+    SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,
+    MachinePointerInfo DstPtrInfo) const {
+  const RISCVSubtarget &Subtarget =
+      DAG.getMachineFunction().getSubtarget<RISCVSubtarget>();
----------------
lenary wrote:

```suggestion
  const auto &Subtarget = DAG.getSubtarget<RISCVSubtarget>();
```

https://github.com/llvm/llvm-project/pull/151555