[llvm] [DAGCombiner] Add combine for vector interleave of splats (PR #151110)
Paul Walker via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 31 03:52:20 PDT 2025
================
@@ -25274,6 +25281,32 @@ static SDValue combineConcatVectorOfShuffleAndItsOperands(
return DAG.getVectorShuffle(VT, dl, ShufOps[0], ShufOps[1], Mask);
}
+static SDValue combineConcatVectorOfSplats(SDNode *N, SelectionDAG &DAG,
+ const TargetLowering &TLI,
+ bool LegalTypes,
+ bool LegalOperations) {
+ EVT VT = N->getValueType(0);
+
+ // Post-legalization we can only create wider SPLAT_VECTOR operations if both
+ // the type and operation is legal. The Hexagon target has custom
+ // legalization for SPLAT_VECTOR that splits the operation into two parts and
+ // concatenates them. Therefore, custom lowering must also be rejected in
+ // order to avoid an infinite loop.
+ if ((LegalTypes && !TLI.isTypeLegal(VT)) ||
+ (LegalOperations && !TLI.isOperationLegal(ISD::SPLAT_VECTOR, VT)))
+ return SDValue();
+
+ if (!llvm::all_equal(N->op_values()) ||
+ N->getOperand(0).getOpcode() != ISD::SPLAT_VECTOR)
+ return SDValue();
+
+ SDValue Splat = DAG.getSplatValue(N->getOperand(0));
+ if (!Splat)
+ return SDValue();
+
+ return DAG.getNode(ISD::SPLAT_VECTOR, SDLoc(N), VT, Splat);
----------------
paulwalker-arm wrote:
Given `N->getOperand(0)` must be a SPLAT_VECTOR.
```suggestion
return DAG.getNode(ISD::SPLAT_VECTOR, SDLoc(N), VT, N->getOperand(0).getOperand(0));
```
https://github.com/llvm/llvm-project/pull/151110
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