[llvm] [AArch64] Improve lowering of scalar abs(sub(a, b)). (PR #151180)

[Paul Walker via llvm-commits]

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@@ -25464,6 +25467,24 @@ static SDValue performCSELCombine(SDNode *N,
     }
   }
 
+  // CSEL a, b, cc, SUBS(SUB(x,y), 0) -> CSEL a, b, cc, SUBS(x,y) if cc doesn't
+  // use overflow flags to avoid the comparison with zero.
+  if (Cond.getOpcode() == AArch64ISD::SUBS &&
+      isNullConstant(Cond.getOperand(1))) {
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paulwalker-arm wrote:

Is it worth having a hasOneUse check here? or perhaps replace `DAG.getNode(AArch64ISD::CSEL...` with `CombineTo(Cond ...`?

That still leaves the possibility of having SUB(x,y) and SUBS(x,y), but that'll be no worse than today, assuming there isn't already code to join them.

https://github.com/llvm/llvm-project/pull/151180