[llvm] [PowerPC] Implement vector unpack instructions (PR #151004)

[Lei Huang via llvm-commits]

================
@@ -45,6 +45,67 @@ multiclass XOForm_RTAB5_L1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
   }
 }
 
+class VXForm_VRTB5<bits<11> xo, bits<5> R, dag OOL, dag IOL, string asmstr,
+                   list<dag> pattern> : I<4, OOL, IOL, asmstr, NoItinerary> {
+  bits<5> VRT;
+  bits<5> VRB;
+
+  let Pattern = pattern;
+
+  let Inst{6 -10} = VRT;
+  let Inst{11 -15} = R;
+  let Inst{16 -20} = VRB;
+  let Inst{21 -31} = xo;
+}
+
+class VXForm_VRTB5_UIM2<bits<11> xo, bits<3> R, dag OOL, dag IOL, string asmstr,
+                        list<dag> pattern>
+    : I<4, OOL, IOL, asmstr, NoItinerary> {
+  bits<5> VRT;
+  bits<5> VRB;
+  bits<2> UIM;
+
+  let Pattern = pattern;
+
+  let Inst{6 -10} = VRT;
+  let Inst{11 -13} = R;
+  let Inst{14 -15} = UIM;
+  let Inst{16 -20} = VRB;
+  let Inst{21 -31} = xo;
+}
+
+class VXForm_VRTB5_UIM1<bits<11> xo, bits<4> R, dag OOL, dag IOL, string asmstr,
+                        list<dag> pattern>
+    : I<4, OOL, IOL, asmstr, NoItinerary> {
+  bits<5> VRT;
+  bits<5> VRB;
+  bits<1> UIM;
+
+  let Pattern = pattern;
+
+  let Inst{6 -10} = VRT;
+  let Inst{11 -14} = R;
+  let Inst{15} = UIM;
+  let Inst{16 -20} = VRB;
+  let Inst{21 -31} = xo;
+}
+
+class VXForm_VRTB5_UIM3<bits<11> xo, bits<2> R, dag OOL, dag IOL, string asmstr,
+                        list<dag> pattern>
+    : I<4, OOL, IOL, asmstr, NoItinerary> {
+  bits<5> VRT;
+  bits<5> VRB;
+  bits<3> UIM;
+
+  let Pattern = pattern;
+
+  let Inst{6 -10} = VRT;
+  let Inst{11 -12} = R;
+  let Inst{13 -15} = UIM;
+  let Inst{16 -20} = VRB;
+  let Inst{21 -31} = xo;
+}
+
----------------
lei137 wrote:

My preference is to keep them separate as the middle bits {11-16} are different combinations of fields for all of them. 

https://github.com/llvm/llvm-project/pull/151004