[llvm] [AArch64] Keep floating-point conversion in SIMD (PR #147707)

[Florian Hahn via llvm-commits]

https://github.com/fhahn commented:

It looks like the patch is causing a crash for the reproducer below:

```
bin/llc reduced.ll
LLVM ERROR: Cannot select: t42: i64 = extract_vector_elt t40, Constant:i64<0>
  t40: v8i16 = AArch64ISD::NVCAST t39
    t39: v2i64 = fp_to_uint t38
      t38: v2f64 = scalar_to_vector t4
        t4: f64 = fadd t2, ConstantFP:f64<2.000000e+00>
          t2: f64,ch = CopyFromReg t0, Register:f64 %3
In function: test
```


```
target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
target triple = "arm64-apple-macosx15.0.0"

declare i1 @cond()

define void @test(ptr %dst, double %0) {
entry:
  br label %loop

loop:
  %ptr.iv = phi ptr [ %dst, %entry ], [ %ptr.iv.next, %loop ]
  %1 = fadd double %0, 2.000000e+00
  %conv137.us.us.us = fptoui double %1 to i64
  %conv142.us.us.us = trunc i64 %conv137.us.us.us to i16
  %ptr.iv.next = getelementptr i8, ptr %ptr.iv, i64 2
  store i16 %conv142.us.us.us, ptr %ptr.iv, align 2
  %c = call i1 @cond()
  br i1 %c, label %loop, label %exit

exit:
  ret void
}
```

https://github.com/llvm/llvm-project/pull/147707