[llvm] [RISCV] Add initial assembler/MC layer support for big-endian (PR #146534)

[Sam Elliott via llvm-commits]

================
@@ -880,6 +882,34 @@ bool RISCVAsmBackend::addReloc(const MCFragment &F, const MCFixup &Fixup,
   return false;
 }
 
+// Data should be swapped for big endian cores.
+static bool isDataFixup(unsigned Kind) {
+  switch (Kind) {
+  default:
+    llvm_unreachable("Unknown fixup kind!");
+
+  case FK_Data_1:
+  case FK_Data_2:
+  case FK_Data_4:
+  case FK_Data_8:
+    return true;
+
+  case RISCV::fixup_riscv_hi20:
+  case RISCV::fixup_riscv_lo12_i:
+  case RISCV::fixup_riscv_lo12_s:
+  case RISCV::fixup_riscv_pcrel_hi20:
+  case RISCV::fixup_riscv_pcrel_lo12_i:
+  case RISCV::fixup_riscv_pcrel_lo12_s:
+  case RISCV::fixup_riscv_jal:
+  case RISCV::fixup_riscv_branch:
+  case RISCV::fixup_riscv_call:
+  case RISCV::fixup_riscv_call_plt:
+  case RISCV::fixup_riscv_rvc_jump:
+  case RISCV::fixup_riscv_rvc_branch:
+    return false;
----------------
lenary wrote:

You're missing a bunch of instruction fixups here:

- `fixup_riscv_12_i`
- `fixup_riscv_rvc_imm`
- `fixup_riscv_qc_e_branch`
- `fixup_riscv_qc_e_32`
- `fixup_riscv_qc_abs20_u`
- `fixup_riscv_qc_e_call_plt`
- `fixup_riscv_nds_branch_10`

https://github.com/llvm/llvm-project/pull/146534