[llvm] [PowerPC][NFC] Refactor PPCInstrFutureMMA.td to combine sections (PR #151194)

[Lei Huang via llvm-commits]

================
@@ -390,7 +391,9 @@ class XX2Form_AT3_XB6_ID2_E1_BL2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
   let Inst{31} = 0;
 }
 
-let Predicates = [IsISAFuture] in {
+//-------------------------- Instruction definitions -------------------------//
+
+let Predicates = [MMA, IsISAFuture] in {
----------------
lei137 wrote:

I think those are meant to be under MMA feature.  That's why it was put into this specific td file, but somehow we missed adding them under the correct predicate sections as multiple was created for the same set of predicates it was hard to see.

Also if you look in `clang/include/clang/Basic/BuiltinsPPC.def` you can see we have a few intrinsics implemented that access `dmr` registers and their required features are set as `"\mma,isa-future-instructions`.

eg:
```
1095 UNALIASED_CUSTOM_BUILTIN(mma_dmsetdmrz, "vW1024*", false,
1096                          "mma,isa-future-instructions")
1097 UNALIASED_CUSTOM_BUILTIN(mma_dmmr, "vW1024*W1024*", false,
1098                          "mma,isa-future-instructions")
1099 UNALIASED_CUSTOM_BUILTIN(mma_dmxor, "vW1024*W1024*", true,
1100                          "mma,isa-future-instructions")
```

https://github.com/llvm/llvm-project/pull/151194