[llvm] [PowerPC] Implement vector uncompress instructions (PR #150702)

[Lei Huang via llvm-commits]

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@@ -45,6 +45,20 @@ multiclass XOForm_RTAB5_L1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
   }
 }
 
+class VXForm_VRTAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
+                    list<dag> pattern> : I<4, OOL, IOL, asmstr, NoItinerary> {
+  bits<5> VRT;
+  bits<5> VRA;
+  bits<5> VRB;
+
+  let Pattern = pattern;
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lei137 wrote:

this should be kept so we can easily add patterns to these instructions definitions in the future when we define intrinsic or identify specific patterns that should be matched to these.

https://github.com/llvm/llvm-project/pull/150702