[llvm] [RISCV] add more generic macrofusions (PR #151140)

[Craig Topper via llvm-commits]

================
@@ -91,3 +91,94 @@ def TuneLDADDFusion
                    CheckIsImmOperand<2>,
                    CheckImmOperand<2, 0>
                  ]>>;
+
+// Fuse add with lw:
+//   add rd, rs1, rs2
+//   lw rd, 0(rd)
+def TuneADDLWFusion
+  : SimpleFusion<"add-lw-fusion", "HasADDLWFusion", "Enable ADD+LW macrofusion",
+                 CheckOpcode<[ADD]>,
+                 CheckAll<[
+                   CheckOpcode<[LW]>,
+                   CheckIsImmOperand<2>,
+                   CheckImmOperand<2, 0>
+                 ]>>;
+
+// Fuse AUIPC followed by LD:
+//   auipc rd, imm20
+//   ld rd, imm12(rd)
+def TuneAUIPCLDFusion
+  : SimpleFusion<"auipc-ld-fusion", "HasAUIPCLDFusion",
+                 "Enable AUIPC+LD macrofusion",
+                 CheckOpcode<[AUIPC]>,
+                 CheckOpcode<[LD]>>;
+
+// Fuse LUI followed by LD:
+//   lui rd, imm[31:12]
+//   ld rd, imm12(rd)
+def TuneLUILDFusion
+  : SimpleFusion<"lui-ld-fusion", "HasLUILDFusion",
+                 "Enable LUI+LD macrofusion",
+                 CheckOpcode<[LUI]>,
+                 CheckOpcode<[LD]>>;
+
+// Bitfield extract fusion: similar to TuneShiftedZExtWFusion
+// but without the immediate restriction
+//   slli rd, rs1, imm12
+//   srli rd, rd, imm12
+def TuneBFExtFusion
+  : SimpleFusion<"bfext-fusion", "HasBFExtFusion",
+                 "Enable SLLI+SRLI (bitfield extract) macrofusion",
+                 CheckAll<[
+                   CheckOpcode<[SLLI]>,
+                   CheckIsImmOperand<2>,
+                 ]>,
+                 CheckAll<[
+                   CheckOpcode<[SRLI]>,
+                   CheckIsImmOperand<2>,
+                 ]>>;
+
+// Fuse ADDI followed by LD
+//   addi rd, rs1, imm12
+//   ld rd, imm12(rd)
+def TuneADDILDFusion
+  : SimpleFusion<"addi-ld-fusion", "HasADDILDFusion",
+                 "Enable ADDI+LD macrofusion",
+                 CheckOpcode<[ADDI]>,
+                 CheckOpcode<[LD]>>;
+
+// Fuse ADDI followed by LW
+//   addi rd, rs1, imm12
+//   lw rd, imm12(rd)
+def TuneADDILWFusion
+  : SimpleFusion<"addi-lw-fusion", "HasADDILWFusion",
+                 "Enable ADDI+LW macrofusion",
+                 CheckOpcode<[ADDI]>,
+                 CheckOpcode<[LW]>>;
+
+// Fuse ADDUW followed by LW
+//   adduw rd, rs1, rs2
+//   lw rd, imm12(rd)
+def TuneADDUWLWFusion
+  : SimpleFusion<"adduw-lw-fusion", "HasADDUWLWFusion",
+                 "Enable ADD_UW+LW macrofusion",
+                 CheckOpcode<[ADD_UW]>,
+                 CheckOpcode<[LW]>>;
+
+// Fuse SHXADD followed by a load (lb, lh, lw, ld)
+//   shXadd rd, rs1, rs2
+//   load rd, imm12(rd)
+def TuneSHXADDLoadFusion
+  : SimpleFusion<"shxadd-load-fusion", "HasSHXADDLoadFusion",
+                 "Enable SH(1|2|3)ADD + load macrofusion",
+                 CheckOpcode<[SH1ADD, SH2ADD, SH3ADD]>,
+                 CheckOpcode<[LB, LH, LW, LD]>>;
+
+// Fuse SHXADD.UW followed by a load (lb, lh, lw, ld)
+//   shXadd.uw rd, rs1, rs2
+//   load rd, imm12(rd)
+def TuneSHXADDUWLoadFusion
+  : SimpleFusion<"shxadduw-load-fusion", "HasSHXADDUWLoadFusion",
+                 "Enable SH(1|2|3)ADDUW + load macrofusion",
+                 CheckOpcode<[SH1ADD_UW, SH2ADD_UW, SH3ADD_UW]>,
+                 CheckOpcode<[LB, LH, LW, LD]>>;
----------------
topperc wrote:

lbu, lhu, lwu?

https://github.com/llvm/llvm-project/pull/151140