[llvm] [AArch64] Keep floating-point conversion in SIMD (PR #147707)

[Paul Walker via llvm-commits]

================
@@ -9264,8 +9273,12 @@ multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,
 
 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,
                          1>;
+defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v4i32, i32, ST1i8_POST,
----------------
paulwalker-arm wrote:

`St1LanePost128Pat` encodes the index as is, so this is only going to be correct for the zero case. This might be reason enough to keep the extra code in the combine.

https://github.com/llvm/llvm-project/pull/147707