[llvm] [LV] Don't consider VPValues without underlying value as generating vectors (PR #150992)

[Luke Lau via llvm-commits]

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@@ -790,65 +790,16 @@ define void @exit_cond_zext_iv(ptr %dst, i64 %N) {
 ; PRED-LABEL: define void @exit_cond_zext_iv(
 ; PRED-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) {
 ; PRED-NEXT:  [[ENTRY:.*]]:
-; PRED-NEXT:    [[UMAX1:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1)
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lukel97 wrote:

Good point, I ended up also needing to add +sve to this test, because without it the masked load always gets scalarized. I've added a new dedicated test in llvm/test/Transforms/LoopVectorize/AArch64/no-vector-instructions.ll

https://github.com/llvm/llvm-project/pull/150992