[llvm] [CostModel/RISCV] Fix costs of vector [l](lrint|lround) (PR #146058)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 29 01:43:19 PDT 2025
================
@@ -1251,11 +1248,41 @@ RISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
switch (ICA.getID()) {
case Intrinsic::lrint:
case Intrinsic::llrint:
- // We can't currently lower half or bfloat vector lrint/llrint.
- if (auto *VecTy = dyn_cast<VectorType>(ICA.getArgTypes()[0]);
- VecTy && VecTy->getElementType()->is16bitFPTy())
- return InstructionCost::getInvalid();
- [[fallthrough]];
+ case Intrinsic::lround:
+ case Intrinsic::llround: {
+ auto LT = getTypeLegalizationCost(RetTy);
+ auto *SrcTy = ICA.getArgTypes().front();
+ auto SrcLT = getTypeLegalizationCost(SrcTy);
+ if (ST->hasVInstructions() && LT.second.isVector()) {
+ ArrayRef<unsigned> Ops;
+ unsigned SrcEltSz =
+ DL.getTypeSizeInBits(cast<VectorType>(SrcTy)->getElementType());
+ unsigned DstEltSz =
+ DL.getTypeSizeInBits(cast<VectorType>(RetTy)->getElementType());
----------------
lukel97 wrote:
```suggestion
DL.getTypeSizeInBits(SrcTy->getScalarType());
unsigned DstEltSz =
DL.getTypeSizeInBits(RetTy->getScalarType());
```
https://github.com/llvm/llvm-project/pull/146058
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