[llvm] [X86][GlobalISel] Improve carry value selection (PR #146586)

via llvm-commits llvm-commits at lists.llvm.org
Tue Jul 29 01:25:03 PDT 2025


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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


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You can test this locally with the following command:
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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
``````````

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<details>
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
index 0def5ff4f..c3bf3fc75 100644
--- a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
+++ b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
@@ -1250,8 +1250,8 @@ bool X86InstructionSelector::selectUAddSub(MachineInstr &I,
            .addReg(Op0Reg)
            .addReg(Op1Reg);
 
-  BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr),
-      CarryOutReg).addImm(X86::COND_B);
+  BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr), CarryOutReg)
+      .addImm(X86::COND_B);
 
   if (!constrainSelectedInstRegOperands(Inst, TII, TRI, RBI) ||
       !RBI.constrainGenericRegister(CarryOutReg, *CarryRC, MRI))

``````````

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https://github.com/llvm/llvm-project/pull/146586


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