[llvm] Handle VECREDUCE intrinsics in NVPTX backend (PR #136253)

[Princeton Ferro via llvm-commits]

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@@ -87,6 +87,10 @@ class NVPTXTTIImpl final : public BasicTTIImplBase<NVPTXTTIImpl> {
   }
   unsigned getMinVectorRegisterBitWidth() const override { return 32; }
 
+  bool shouldExpandReduction(const IntrinsicInst *II) const override {
+    return false;
+  }
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Prince781 wrote:

I added a comment in this area now:

https://github.com/Prince781/llvm-project/blob/f4f7fe14a94a01cf42925e7f463a5f670ff6b744/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h#L90-L95

https://github.com/llvm/llvm-project/pull/136253