[llvm] [DAG] Always use stack to promote bitcast when the source is vector (PR #151065)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 28 17:53:41 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-selectiondag
@llvm/pr-subscribers-backend-amdgpu
Author: Min-Yih Hsu (mshockwave)
<details>
<summary>Changes</summary>
The optimization introduced by #<!-- -->125637 tried to avoid using stacks to promote bitcast with vector result type. However, it wouldn't be correct if the input type is vector. This patch limits that optimizations to only scalar to vector bitcasts.
------
A counter example for the original patch: https://github.com/llvm/llvm-project/pull/125637#issuecomment-3130134005
---
Patch is 265.26 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/151065.diff
11 Files Affected:
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (+2-1)
- (modified) llvm/test/CodeGen/AMDGPU/ctpop16.ll (+275-55)
- (modified) llvm/test/CodeGen/AMDGPU/kernel-args.ll (+611-122)
- (modified) llvm/test/CodeGen/AMDGPU/load-constant-i16.ll (+23-17)
- (modified) llvm/test/CodeGen/AMDGPU/load-constant-i8.ll (+1105-195)
- (modified) llvm/test/CodeGen/AMDGPU/load-global-i16.ll (+45-34)
- (modified) llvm/test/CodeGen/AMDGPU/load-global-i8.ll (+2201-394)
- (modified) llvm/test/CodeGen/AMDGPU/load-local-i16.ll (+16-8)
- (modified) llvm/test/CodeGen/AMDGPU/min.ll (+231-75)
- (modified) llvm/test/CodeGen/AMDGPU/shl.ll (+46-13)
- (modified) llvm/test/CodeGen/AMDGPU/sra.ll (+53-14)
``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 583a85a332dcd..0bd0599692bcc 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -2218,7 +2218,8 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
switch (getTypeAction(InVT)) {
case TargetLowering::TypePromoteInteger: {
// TODO: Handle big endian
- if (OutVT.isVector() && DAG.getDataLayout().isLittleEndian()) {
+ if (OutVT.isVector() && !InVT.isVector() &&
+ DAG.getDataLayout().isLittleEndian()) {
EVT EltVT = OutVT.getVectorElementType();
TypeSize EltSize = EltVT.getSizeInBits();
TypeSize NInSize = NInVT.getSizeInBits();
diff --git a/llvm/test/CodeGen/AMDGPU/ctpop16.ll b/llvm/test/CodeGen/AMDGPU/ctpop16.ll
index 1b9b508137b7f..cefcbddd3e394 100644
--- a/llvm/test/CodeGen/AMDGPU/ctpop16.ll
+++ b/llvm/test/CodeGen/AMDGPU/ctpop16.ll
@@ -457,27 +457,58 @@ define amdgpu_kernel void @v_ctpop_v4i16(ptr addrspace(1) noalias %out, ptr addr
;
; EG-LABEL: v_ctpop_v4i16:
; EG: ; %bb.0:
-; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: ALU 3, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
-; EG-NEXT: ALU 7, @11, KC0[CB0:0-32], KC1[]
-; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T6.X, 1
+; EG-NEXT: ALU 37, @12, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XY, T0.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: Fetch clause starting at 6:
-; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
+; EG-NEXT: VTX_READ_64 T8.XY, T0.X, 0, #1
; EG-NEXT: ALU clause starting at 8:
-; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
+; EG-NEXT: MOV T0.Y, T4.X,
+; EG-NEXT: LSHL * T0.W, T0.X, literal.x, BS:VEC_120/SCL_212
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,
-; EG-NEXT: ALU clause starting at 11:
-; EG-NEXT: LSHR * T0.W, T0.X, literal.x,
+; EG-NEXT: ALU clause starting at 12:
+; EG-NEXT: AND_INT * T0.W, T8.X, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: BCNT_INT T0.W, PV.W,
+; EG-NEXT: AND_INT * T1.W, T0.Y, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: MOV * T4.X, PV.W,
+; EG-NEXT: MOV T0.X, PV.X,
+; EG-NEXT: LSHR * T0.W, T8.X, literal.x,
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
-; EG-NEXT: BCNT_INT T0.Y, PV.W,
-; EG-NEXT: AND_INT * T0.W, T0.X, literal.x,
+; EG-NEXT: BCNT_INT T0.W, PV.W,
+; EG-NEXT: AND_INT * T1.W, PV.X, literal.x,
; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
-; EG-NEXT: BCNT_INT T0.X, PV.W,
-; EG-NEXT: LSHR * T6.X, KC0[2].Y, literal.x,
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV T4.X, PV.W,
+; EG-NEXT: MOV * T0.X, T5.X,
+; EG-NEXT: AND_INT * T0.W, T8.Y, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: BCNT_INT T0.W, PV.W,
+; EG-NEXT: AND_INT * T1.W, T0.X, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: MOV * T5.X, PV.W,
+; EG-NEXT: MOV T0.X, PV.X,
+; EG-NEXT: LSHR * T0.W, T8.Y, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BCNT_INT T0.W, PV.W,
+; EG-NEXT: AND_INT * T1.W, PV.X, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
+; EG-NEXT: OR_INT * T8.Y, T1.W, PV.W,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: MOV T5.X, PV.Y,
+; EG-NEXT: MOV * T8.X, T4.X,
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%in.gep = getelementptr <4 x i16>, ptr addrspace(1) %in, i32 %tid
%val = load <4 x i16>, ptr addrspace(1) %in.gep, align 16
@@ -570,33 +601,94 @@ define amdgpu_kernel void @v_ctpop_v8i16(ptr addrspace(1) noalias %out, ptr addr
;
; EG-LABEL: v_ctpop_v8i16:
; EG: ; %bb.0:
-; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: ALU 3, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
-; EG-NEXT: ALU 13, @11, KC0[CB0:0-32], KC1[]
-; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T8.X, 1
+; EG-NEXT: ALU 73, @12, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T12.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: Fetch clause starting at 6:
-; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
+; EG-NEXT: VTX_READ_128 T12.XYZW, T0.X, 0, #1
; EG-NEXT: ALU clause starting at 8:
-; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
+; EG-NEXT: MOV T0.Y, T4.X,
+; EG-NEXT: LSHL * T0.W, T0.X, literal.x, BS:VEC_120/SCL_212
; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00)
; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,
-; EG-NEXT: ALU clause starting at 11:
-; EG-NEXT: LSHR * T0.W, T0.Z, literal.x,
+; EG-NEXT: ALU clause starting at 12:
+; EG-NEXT: LSHR * T0.W, T12.X, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BCNT_INT * T0.W, PV.W,
+; EG-NEXT: LSHL T0.W, PV.W, literal.x,
+; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,
+; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41)
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: MOV * T4.X, PV.W,
+; EG-NEXT: MOV T0.X, PV.X,
+; EG-NEXT: AND_INT * T0.W, T12.X, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: BCNT_INT T0.W, PV.W,
+; EG-NEXT: AND_INT * T1.W, PV.X, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: MOV T4.X, PV.W,
+; EG-NEXT: MOV * T0.X, T5.X,
+; EG-NEXT: LSHR * T0.W, T12.Y, literal.x,
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
; EG-NEXT: BCNT_INT T0.W, PV.W,
-; EG-NEXT: AND_INT * T1.W, T0.Z, literal.x,
+; EG-NEXT: AND_INT * T1.W, T0.X, literal.x,
; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
-; EG-NEXT: BCNT_INT T0.Z, PS,
-; EG-NEXT: LSHR * T1.W, T0.X, literal.x,
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV * T5.X, PV.W,
+; EG-NEXT: MOV T0.X, PV.X,
+; EG-NEXT: AND_INT * T0.W, T12.Y, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: BCNT_INT T0.W, PV.W,
+; EG-NEXT: AND_INT * T1.W, PV.X, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.Y, PS, PV.W,
+; EG-NEXT: MOV T5.X, PV.Y,
+; EG-NEXT: MOV * T0.X, T8.X,
+; EG-NEXT: LSHR * T0.W, T12.Z, literal.x,
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
-; EG-NEXT: BCNT_INT T0.Y, PV.W,
+; EG-NEXT: BCNT_INT T0.W, PV.W,
; EG-NEXT: AND_INT * T1.W, T0.X, literal.x,
; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
-; EG-NEXT: BCNT_INT T0.X, PV.W,
-; EG-NEXT: LSHR * T8.X, KC0[2].Y, literal.x,
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV * T8.X, PV.W,
+; EG-NEXT: MOV T0.X, PV.X,
+; EG-NEXT: AND_INT * T0.W, T12.Z, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: BCNT_INT T0.W, PV.W,
+; EG-NEXT: AND_INT * T1.W, PV.X, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: MOV T8.X, PV.W,
+; EG-NEXT: MOV * T0.X, T9.X,
+; EG-NEXT: LSHR * T0.W, T12.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BCNT_INT T0.W, PV.W,
+; EG-NEXT: AND_INT * T1.W, T0.X, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV * T9.X, PV.W,
+; EG-NEXT: MOV T0.X, PV.X,
+; EG-NEXT: AND_INT * T0.W, T12.W, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: BCNT_INT T0.W, PV.W,
+; EG-NEXT: AND_INT * T1.W, PV.X, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: LSHR T12.X, KC0[2].Y, literal.x,
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: MOV T9.X, PV.W,
+; EG-NEXT: MOV * T0.X, T4.X,
+; EG-NEXT: MOV * T0.Z, T8.X,
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%in.gep = getelementptr <8 x i16>, ptr addrspace(1) %in, i32 %tid
%val = load <8 x i16>, ptr addrspace(1) %in.gep, align 32
@@ -745,46 +837,174 @@ define amdgpu_kernel void @v_ctpop_v16i16(ptr addrspace(1) noalias %out, ptr add
;
; EG-LABEL: v_ctpop_v16i16:
; EG: ; %bb.0:
-; EG-NEXT: ALU 2, @10, KC0[CB0:0-32], KC1[]
-; EG-NEXT: TEX 1 @6
-; EG-NEXT: ALU 25, @13, KC0[CB0:0-32], KC1[]
-; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T14.X, 0
-; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T13.X, 1
+; EG-NEXT: ALU 3, @12, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 1 @8
+; EG-NEXT: ALU 114, @16, KC0[], KC1[]
+; EG-NEXT: ALU 34, @131, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T22.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T20.XYZW, T21.X, 1
; EG-NEXT: CF_END
-; EG-NEXT: Fetch clause starting at 6:
-; EG-NEXT: VTX_READ_128 T12.XYZW, T0.X, 16, #1
-; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
-; EG-NEXT: ALU clause starting at 10:
-; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 8:
+; EG-NEXT: VTX_READ_128 T20.XYZW, T0.X, 16, #1
+; EG-NEXT: VTX_READ_128 T21.XYZW, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 12:
+; EG-NEXT: MOV T0.Y, T4.X,
+; EG-NEXT: LSHL * T0.W, T0.X, literal.x, BS:VEC_120/SCL_212
; EG-NEXT: 5(7.006492e-45), 0(0.000000e+00)
; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,
-; EG-NEXT: ALU clause starting at 13:
-; EG-NEXT: LSHR * T0.W, T12.Z, literal.x,
+; EG-NEXT: ALU clause starting at 16:
+; EG-NEXT: LSHR * T0.W, T20.X, literal.x,
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
-; EG-NEXT: BCNT_INT T12.W, PV.W,
-; EG-NEXT: AND_INT * T0.W, T12.Z, literal.x,
+; EG-NEXT: BCNT_INT * T0.W, PV.W,
+; EG-NEXT: LSHL T0.W, PV.W, literal.x,
+; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,
+; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41)
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: MOV * T4.X, PV.W,
+; EG-NEXT: MOV T0.X, PV.X,
+; EG-NEXT: AND_INT * T0.W, T20.X, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: BCNT_INT T0.W, PV.W,
+; EG-NEXT: AND_INT * T1.W, PV.X, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: MOV T4.X, PV.W,
+; EG-NEXT: MOV * T0.X, T5.X,
+; EG-NEXT: LSHR * T0.W, T20.Y, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BCNT_INT T0.W, PV.W,
+; EG-NEXT: AND_INT * T1.W, T0.X, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV * T5.X, PV.W,
+; EG-NEXT: MOV T0.X, PV.X,
+; EG-NEXT: AND_INT * T0.W, T20.Y, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: BCNT_INT T0.W, PV.W,
+; EG-NEXT: AND_INT * T1.W, PV.X, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.Y, PS, PV.W,
+; EG-NEXT: MOV T5.X, PV.Y,
+; EG-NEXT: MOV * T0.X, T8.X,
+; EG-NEXT: LSHR * T0.W, T20.Z, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BCNT_INT T0.W, PV.W,
+; EG-NEXT: AND_INT * T1.W, T0.X, literal.x,
; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
-; EG-NEXT: BCNT_INT T12.Z, PS,
-; EG-NEXT: LSHR T0.W, T0.Z, literal.x,
-; EG-NEXT: LSHR * T1.W, T12.X, literal.x,
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV * T8.X, PV.W,
+; EG-NEXT: MOV T0.X, PV.X,
+; EG-NEXT: AND_INT * T0.W, T20.Z, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: BCNT_INT T0.W, PV.W,
+; EG-NEXT: AND_INT * T1.W, PV.X, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: MOV T8.X, PV.W,
+; EG-NEXT: MOV * T0.X, T9.X,
+; EG-NEXT: LSHR * T0.W, T20.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BCNT_INT T0.W, PV.W,
+; EG-NEXT: AND_INT * T1.W, T0.X, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
-; EG-NEXT: BCNT_INT T12.Y, PS,
-; EG-NEXT: AND_INT T0.Z, T0.Z, literal.x,
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV * T9.X, PV.W,
+; EG-NEXT: MOV T0.X, PV.X,
+; EG-NEXT: AND_INT * T0.W, T20.W, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
; EG-NEXT: BCNT_INT T0.W, PV.W,
-; EG-NEXT: AND_INT * T1.W, T12.X, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.X, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: MOV T9.X, PV.W,
+; EG-NEXT: MOV * T0.X, T12.X,
+; EG-NEXT: LSHR * T1.W, T21.X, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BCNT_INT T1.W, PV.W,
+; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: LSHL * T1.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T1.W, T2.W, PV.W,
+; EG-NEXT: MOV * T12.X, PV.W,
+; EG-NEXT: MOV T0.X, PV.X,
+; EG-NEXT: AND_INT * T1.W, T21.X, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: BCNT_INT T1.W, PV.W,
+; EG-NEXT: AND_INT * T2.W, PV.X, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T1.W, PS, PV.W,
+; EG-NEXT: MOV T12.X, PV.W,
+; EG-NEXT: MOV * T0.X, T13.X,
+; EG-NEXT: LSHR * T1.W, T21.Y, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BCNT_INT T1.W, PV.W,
+; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: LSHL * T1.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T1.W, T2.W, PV.W,
+; EG-NEXT: MOV * T13.X, PV.W,
+; EG-NEXT: MOV T0.X, PV.X,
+; EG-NEXT: AND_INT * T1.W, T21.Y, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: BCNT_INT T1.W, PV.W,
+; EG-NEXT: AND_INT * T2.W, PV.X, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T20.Y, PS, PV.W,
+; EG-NEXT: MOV T13.X, PV.Y,
+; EG-NEXT: MOV * T0.X, T16.X,
+; EG-NEXT: LSHR * T1.W, T21.Z, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BCNT_INT T1.W, PV.W,
+; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: LSHL * T1.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T1.W, T2.W, PV.W,
+; EG-NEXT: ALU clause starting at 131:
+; EG-NEXT: MOV * T16.X, T1.W,
+; EG-NEXT: MOV T0.X, PV.X,
+; EG-NEXT: AND_INT * T1.W, T21.Z, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: BCNT_INT T1.W, PV.W,
+; EG-NEXT: AND_INT * T2.W, PV.X, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T1.W, PS, PV.W,
+; EG-NEXT: MOV T16.X, PV.W,
+; EG-NEXT: MOV * T0.X, T17.X,
+; EG-NEXT: LSHR * T1.W, T21.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BCNT_INT T1.W, PV.W,
+; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,
; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
-; EG-NEXT: BCNT_INT T12.X, PS,
-; EG-NEXT: BCNT_INT T0.Z, PV.Z,
-; EG-NEXT: LSHR T1.W, T0.X, literal.x,
-; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x,
+; EG-NEXT: LSHL * T1.W, PV.W, literal.x,
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
-; EG-NEXT: LSHR T13.X, PS, literal.x,
-; EG-NEXT: BCNT_INT T0.Y, PV.W,
-; EG-NEXT: AND_INT * T1.W, T0.X, literal.y,
-; EG-NEXT: 2(2.802597e-45), 65535(9.183409e-41)
-; EG-NEXT: BCNT_INT T0.X, PV.W,
-; EG-NEXT: LSHR * T14.X, KC0[2].Y, literal.x,
+; EG-NEXT: OR_INT * T1.W, T2.W, PV.W,
+; EG-NEXT: MOV * T17.X, PV.W,
+; EG-NEXT: MOV T0.X, PV.X,
+; EG-NEXT: AND_INT T1.W, T21.W, literal.x,
+; EG-NEXT: LSHR * T21.X, KC0[2].Y, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 2(2.802597e-45)
+; EG-NEXT: AND_INT T0.Z, PV.X, literal.x,
+; EG-NEXT: BCNT_INT T1.W, PV.W,
+; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.y,
+; EG-NEXT: -65536(nan), 16(2.242078e-44)
+; EG-NEXT: LSHR T22.X, PS, literal.x,
+; EG-NEXT: OR_INT * T20.W, PV.Z, PV.W,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: MOV T17.X, PV.W,
+; EG-NEXT: MOV * T0.X, T4.X,
+; EG-NEXT: MOV * T0.Z, T8.X,
+; EG-NEXT: MOV T20.X, T12.X,
+; EG-NEXT: MOV * T20.Z, T16.X, BS:VEC_120/SCL_212
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%in.gep = getelementptr <16 x i16>, ptr addrspace(1) %in, i32 %tid
%val = load <16 x i16>, ptr addrspace(1) %in.gep, align 32
@@ -1292,7 +1512,7 @@ define amdgpu_kernel void @ctpop_i16_in_br(ptr addrspace(1) %out, ptr addrspace(
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
; SI-NEXT: .LBB14_4:
-; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: s_branch .LBB14_2
;
; VI-LABEL: ctpop_i16_in_br:
diff --git a/llvm/test/CodeGen/AMDGPU/kernel-args.ll b/llvm/test/CodeGen/AMDGPU/kernel-args.ll
index bad2e603f22e7..a2da8876472ab 100644
--- a/llvm/test/CodeGen/AMDGPU/kernel-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/kernel-args.ll
@@ -1025,67 +1025,74 @@ define amdgpu_kernel void @v3i16_arg(ptr addrspace(1) nocapture %out, <3 x i16>
;
; EG-LABEL: v3i16_arg:
; EG: ; %bb.0: ; %entry
-; EG-NEXT: ALU 0, @10, KC0[], KC1[]
-; EG-NEXT: TEX 1 @6
-; EG-NEXT: ALU 14, @11, KC0[CB0:0-32], KC1[]
-; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T3.X, 0
-; EG-NEXT: MEM_RAT MSKOR T2.XW, T0.X
+; EG-NEXT: ALU 0, @12, KC0[], KC1[]
+; EG-NEXT: TEX 2 @6
+; EG-NEXT: ALU 19, @13, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.X, T7.X, 0
+; EG-NEXT: MEM_RAT MSKOR T5.XW, T8.X
; EG-NEXT: CF_END
; EG-NEXT: Fetch clause starting at 6:
-; EG-NEXT: VTX_READ_16 T1.X, T0.X, 44, #3
-; EG-NEXT: VTX_READ_16 T0.X, T0.X, 48, #3
-; EG-NEXT: ALU clause starting at 10:
-; EG-NEXT: MOV * T0.X, 0.0,
-; EG-NEXT: ALU clause starting at 11:
+; EG-NEXT: VTX_READ_16 T6.X, T5.X, 44, #3
+; EG-NEXT: VTX_READ_16 T7.X, T5.X, 46, #3
+; EG-NEXT: VTX_READ_16 T5.X, T5.X, 48, #3
+; EG-NEXT: ALU clause starting at 12:
+; EG-NEXT: MOV * T5.X, 0.0,
+; EG-NEXT: ALU clause starting at 13:
; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00)
; EG-NEXT: AND_INT T1.W, PV.W, literal.x,
-; EG-NEXT: AND_INT * T2.W, T0.X, literal.y,
+; EG-NEXT: AND_INT * T2.W, T5.X, literal.y,
; EG-NEXT: 3(4.203895e-45), 65535(9.183409e-41)
; EG-NEXT: LSHL * T1.W, PV.W, literal.x,
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
-; EG-NEXT: LSHL T2.X, T2.W, PV.W,
-; EG-NEXT: LSHL * T2.W, literal.x, PV.W,
+; EG-NEXT: LSHL T5.X, T2.W, PV.W,
+; EG-NEXT: LSHL * T5.W, literal.x, PV.W,
; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
-; EG-NEXT: MOV T2.Y, 0.0,
-; EG-NEXT: MOV * T2.Z, 0.0,
-; EG-NEXT: LSHR T0.X, T0.W, literal.x,
-; EG-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,
+; EG-NEXT: MOV T5.Y, 0.0,
+; EG-NEXT: MOV * T5.Z, 0.0,
+; EG-NEXT: LSHR T8.X, T0.W, literal.x,
+; EG-NEXT: LSHL T0.W, T7.X, literal.y,
+; EG-NEXT: AND_INT * T1.W, T6.X, literal.z,
+; EG-NEXT: 2(2.802597e-...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/151065
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