[llvm] [AMDGPU] Optimize away v_readfirstlane_b32 on SGPR input (PR #151033)

[Shilei Tian via llvm-commits]

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@@ -6382,6 +6382,67 @@ void SIInstrInfo::legalizeOperandsVOP3(MachineRegisterInfo &MRI,
     legalizeOpWithMove(MI, VOP3Idx[2]);
 }
 
+// Recursively check to see if the ultimate source of a readfirstlane is SGPR.
+// If it is, readfirstlane can be omitted, and the source of the value can be
+// used directly.
+Register SIInstrInfo::checkIsSourceSGPR(const MachineOperand &MO,
+                                        const MachineRegisterInfo &MRI,
+                                        const SIRegisterInfo *TRI,
+                                        int MaxDepth) const {
+  if (MaxDepth == 0)
+    return Register();
+
+  Register PotentialSGPR = MO.getReg();
+
+  // While we could return a physical SGPR source, we would need to guarantee it
+  // has not been redefined.
+  if (PotentialSGPR.isPhysical())
+    return Register();
+
+  assert(MRI.hasOneDef(PotentialSGPR));
+
+  MachineInstr *MI = MRI.getVRegDef(PotentialSGPR);
+  auto MIOpc = MI->getOpcode();
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shiltian wrote:

no auto

https://github.com/llvm/llvm-project/pull/151033