[llvm] [RISCV] Support PreserveMost calling convention (PR #148214)

[Sam Elliott via llvm-commits]

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@@ -413,6 +413,8 @@ added in the future:
     - On AArch64 the callee preserve all general purpose registers, except
       X0-X8 and X16-X18. Not allowed with ``nest``.
 
+    - On RISC-V the callee preserve x5-x31 registers.
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lenary wrote:

This looks right, I think. Can you add a test where one of those `t1-t3` registers is clobbered in the function, to show it will be saved? I'm not quite sure the correct way to do this, maybe a `%1 = load volatile [32 x i64], ptr @var; store volatile [32 x i64] %1, ptr @var` like in llvm/test/CodeGen/RISCV/reserved-regs.ll

https://github.com/llvm/llvm-project/pull/148214