[llvm] [RISCV] Cost bf16/f16 vector non-unit memory accesses as legal without zvfhmin/zvfbfmin (PR #150882)

[Luke Lau via llvm-commits]

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@@ -21,6 +22,52 @@ define void @fadd(ptr noalias %a, ptr noalias %b, i64 %n) {
 ; NO-ZVFBFMIN:       [[EXIT]]:
 ; NO-ZVFBFMIN-NEXT:    ret void
 ;
+; NO-ZVFBFMIN-PREDICATED-LABEL: define void @fadd(
+; NO-ZVFBFMIN-PREDICATED-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
+; NO-ZVFBFMIN-PREDICATED-NEXT:  [[ENTRY:.*]]:
+; NO-ZVFBFMIN-PREDICATED-NEXT:    br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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lukel97 wrote:

The test should be fixed with 5f2092dae36486f428485e47b9a694463c855a4e, it was due to the interaction with #150908. 

It shouldn't be vectorized because all the actual recipes with underlying instructions get scalarized, since there's no vector bf16 support. 

I think there's a separate issue with tail folding where things like VPWidenCanonicalIVRecipe can end up counting as "emitting vector instructions", despite not being in the original IR. I think we need to check `getUnderlyingValue()` in `willGenerateVectors`

https://github.com/llvm/llvm-project/pull/150882