[llvm] [SelectionDAG] Detect impossible conditions using known bits analysis (PR #150715)

[Simon Pilgrim via llvm-commits]

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@@ -13529,6 +13529,78 @@ SDValue DAGCombiner::visitSETCC(SDNode *N) {
   SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
   SDLoc DL(N);
 
+  // Detect impossible conditions using known bits analysis.
+  if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1)) {
+    const APInt &C1 = N1C->getAPIntValue();
+    KnownBits KnownRHS = KnownBits::makeConstant(C1);
+
+    // Bail out early if RHS is unknown (shouldn't happen for constants)
+    if (KnownRHS.isUnknown())
+      return SDValue();
+
+    std::optional<bool> KnownVal;
+
+    // Handle special cases first (like GlobalISel does)
+    if (KnownRHS.isZero()) {
+      // x >=u 0 -> always true
+      // x <u 0 -> always false
+      if (Cond == ISD::SETUGE)
+        KnownVal = true;
+      else if (Cond == ISD::SETULT)
+        KnownVal = false;
+    }
+
+    if (!KnownVal) {
+      bool SupportedPredicate = true;
+      KnownBits KnownLHS = DAG.computeKnownBits(N0);
+
+      // Convert ISD::CondCode to CmpInst::Predicate
+      CmpInst::Predicate Pred;
+      switch (Cond) {
+      case ISD::SETEQ:
+        Pred = CmpInst::ICMP_EQ;
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RKSimon wrote:

Do we have an existing ISD::CondCode ->  CmpInst::Predicate helper we can use? Or we just call the KnownBits compares directly in the switch

https://github.com/llvm/llvm-project/pull/150715