[llvm] [ARM] Only forbid PL if using vselect (PR #150781)
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Sat Jul 26 10:34:13 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-arm
Author: AZero13 (AZero13)
<details>
<summary>Changes</summary>
Otherwise there is no reason to prevent it.
---
Full diff: https://github.com/llvm/llvm-project/pull/150781.diff
4 Files Affected:
- (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+3-1)
- (modified) llvm/test/CodeGen/ARM/consthoist-icmpimm.ll (+16-16)
- (modified) llvm/test/CodeGen/ARM/select-constant-xor.ll (+2-2)
- (modified) llvm/test/CodeGen/Thumb/smul_fix_sat.ll (+1-1)
``````````diff
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 6b85e62d2eb8b..cc7e51fe0c288 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -5610,6 +5610,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
// inverting the compare condition, swapping 'less' and 'greater') and
// sometimes need to swap the operands to the VSEL (which inverts the
// condition in the sense of firing whenever the previous condition didn't)
+ bool CanUsePL = true;
if (Subtarget->hasFPARMv8Base() && (TrueVal.getValueType() == MVT::f16 ||
TrueVal.getValueType() == MVT::f32 ||
TrueVal.getValueType() == MVT::f64)) {
@@ -5619,12 +5620,13 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
CC = ISD::getSetCCInverse(CC, LHS.getValueType());
std::swap(TrueVal, FalseVal);
}
+ CanUsePL = false;
}
SDValue ARMcc;
SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
// Choose GE over PL, which vsel does now support
- if (ARMcc->getAsZExtVal() == ARMCC::PL)
+ if (!CanUsePL && ARMcc->getAsZExtVal() == ARMCC::PL)
ARMcc = DAG.getConstant(ARMCC::GE, dl, MVT::i32);
return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, Cmp, DAG);
}
diff --git a/llvm/test/CodeGen/ARM/consthoist-icmpimm.ll b/llvm/test/CodeGen/ARM/consthoist-icmpimm.ll
index 16b7403bdb932..fc0f9b6c16700 100644
--- a/llvm/test/CodeGen/ARM/consthoist-icmpimm.ll
+++ b/llvm/test/CodeGen/ARM/consthoist-icmpimm.ll
@@ -14,16 +14,16 @@ define i32 @icmp64_sge_0(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV6M-NEXT: @ %bb.1: @ %then
; CHECKV6M-NEXT: cmp r3, #0
; CHECKV6M-NEXT: mov r3, r0
-; CHECKV6M-NEXT: blt .LBB0_7
+; CHECKV6M-NEXT: bmi .LBB0_7
; CHECKV6M-NEXT: @ %bb.2: @ %then
; CHECKV6M-NEXT: cmp r1, #0
-; CHECKV6M-NEXT: blt .LBB0_8
+; CHECKV6M-NEXT: bmi .LBB0_8
; CHECKV6M-NEXT: .LBB0_3: @ %then
; CHECKV6M-NEXT: adds r0, r0, r3
; CHECKV6M-NEXT: bx lr
; CHECKV6M-NEXT: .LBB0_4: @ %else
; CHECKV6M-NEXT: cmp r1, #0
-; CHECKV6M-NEXT: bge .LBB0_6
+; CHECKV6M-NEXT: bpl .LBB0_6
; CHECKV6M-NEXT: @ %bb.5: @ %else
; CHECKV6M-NEXT: mov r0, r2
; CHECKV6M-NEXT: .LBB0_6: @ %else
@@ -31,7 +31,7 @@ define i32 @icmp64_sge_0(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV6M-NEXT: .LBB0_7: @ %then
; CHECKV6M-NEXT: mov r3, r2
; CHECKV6M-NEXT: cmp r1, #0
-; CHECKV6M-NEXT: bge .LBB0_3
+; CHECKV6M-NEXT: bpl .LBB0_3
; CHECKV6M-NEXT: .LBB0_8: @ %then
; CHECKV6M-NEXT: mov r0, r2
; CHECKV6M-NEXT: adds r0, r0, r3
@@ -105,16 +105,16 @@ define i32 @icmp64_sgt_m1(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV6M-NEXT: @ %bb.1: @ %then
; CHECKV6M-NEXT: cmp r3, #0
; CHECKV6M-NEXT: mov r3, r0
-; CHECKV6M-NEXT: blt .LBB1_7
+; CHECKV6M-NEXT: bmi .LBB1_7
; CHECKV6M-NEXT: @ %bb.2: @ %then
; CHECKV6M-NEXT: cmp r1, #0
-; CHECKV6M-NEXT: blt .LBB1_8
+; CHECKV6M-NEXT: bmi .LBB1_8
; CHECKV6M-NEXT: .LBB1_3: @ %then
; CHECKV6M-NEXT: adds r0, r0, r3
; CHECKV6M-NEXT: bx lr
; CHECKV6M-NEXT: .LBB1_4: @ %else
; CHECKV6M-NEXT: cmp r3, #0
-; CHECKV6M-NEXT: bge .LBB1_6
+; CHECKV6M-NEXT: bpl .LBB1_6
; CHECKV6M-NEXT: @ %bb.5: @ %else
; CHECKV6M-NEXT: mov r0, r2
; CHECKV6M-NEXT: .LBB1_6: @ %else
@@ -122,7 +122,7 @@ define i32 @icmp64_sgt_m1(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV6M-NEXT: .LBB1_7: @ %then
; CHECKV6M-NEXT: mov r3, r2
; CHECKV6M-NEXT: cmp r1, #0
-; CHECKV6M-NEXT: bge .LBB1_3
+; CHECKV6M-NEXT: bpl .LBB1_3
; CHECKV6M-NEXT: .LBB1_8: @ %then
; CHECKV6M-NEXT: mov r0, r2
; CHECKV6M-NEXT: adds r0, r0, r3
@@ -196,16 +196,16 @@ define i32 @icmp32_sge_0(i32 %x, i32 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV6M-NEXT: @ %bb.1: @ %then
; CHECKV6M-NEXT: cmp r1, #0
; CHECKV6M-NEXT: mov r1, r2
-; CHECKV6M-NEXT: blt .LBB2_7
+; CHECKV6M-NEXT: bmi .LBB2_7
; CHECKV6M-NEXT: @ %bb.2: @ %then
; CHECKV6M-NEXT: cmp r0, #0
-; CHECKV6M-NEXT: blt .LBB2_8
+; CHECKV6M-NEXT: bmi .LBB2_8
; CHECKV6M-NEXT: .LBB2_3: @ %then
; CHECKV6M-NEXT: adds r0, r2, r1
; CHECKV6M-NEXT: pop {r4, pc}
; CHECKV6M-NEXT: .LBB2_4: @ %else
; CHECKV6M-NEXT: cmp r0, #0
-; CHECKV6M-NEXT: bge .LBB2_6
+; CHECKV6M-NEXT: bpl .LBB2_6
; CHECKV6M-NEXT: @ %bb.5: @ %else
; CHECKV6M-NEXT: mov r2, r3
; CHECKV6M-NEXT: .LBB2_6: @ %else
@@ -214,7 +214,7 @@ define i32 @icmp32_sge_0(i32 %x, i32 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV6M-NEXT: .LBB2_7: @ %then
; CHECKV6M-NEXT: mov r1, r3
; CHECKV6M-NEXT: cmp r0, #0
-; CHECKV6M-NEXT: bge .LBB2_3
+; CHECKV6M-NEXT: bpl .LBB2_3
; CHECKV6M-NEXT: .LBB2_8: @ %then
; CHECKV6M-NEXT: mov r2, r3
; CHECKV6M-NEXT: adds r0, r2, r1
@@ -290,16 +290,16 @@ define i32 @icmp32_sgt_m1(i32 %x, i32 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV6M-NEXT: @ %bb.1: @ %then
; CHECKV6M-NEXT: cmp r1, #0
; CHECKV6M-NEXT: mov r1, r2
-; CHECKV6M-NEXT: blt .LBB3_7
+; CHECKV6M-NEXT: bmi .LBB3_7
; CHECKV6M-NEXT: @ %bb.2: @ %then
; CHECKV6M-NEXT: cmp r0, #0
-; CHECKV6M-NEXT: blt .LBB3_8
+; CHECKV6M-NEXT: bmi .LBB3_8
; CHECKV6M-NEXT: .LBB3_3: @ %then
; CHECKV6M-NEXT: adds r0, r2, r1
; CHECKV6M-NEXT: pop {r4, pc}
; CHECKV6M-NEXT: .LBB3_4: @ %else
; CHECKV6M-NEXT: cmp r1, #0
-; CHECKV6M-NEXT: bge .LBB3_6
+; CHECKV6M-NEXT: bpl .LBB3_6
; CHECKV6M-NEXT: @ %bb.5: @ %else
; CHECKV6M-NEXT: mov r2, r3
; CHECKV6M-NEXT: .LBB3_6: @ %else
@@ -308,7 +308,7 @@ define i32 @icmp32_sgt_m1(i32 %x, i32 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV6M-NEXT: .LBB3_7: @ %then
; CHECKV6M-NEXT: mov r1, r3
; CHECKV6M-NEXT: cmp r0, #0
-; CHECKV6M-NEXT: bge .LBB3_3
+; CHECKV6M-NEXT: bpl .LBB3_3
; CHECKV6M-NEXT: .LBB3_8: @ %then
; CHECKV6M-NEXT: mov r2, r3
; CHECKV6M-NEXT: adds r0, r2, r1
diff --git a/llvm/test/CodeGen/ARM/select-constant-xor.ll b/llvm/test/CodeGen/ARM/select-constant-xor.ll
index 543ddcd3efac9..cce20f669bafb 100644
--- a/llvm/test/CodeGen/ARM/select-constant-xor.ll
+++ b/llvm/test/CodeGen/ARM/select-constant-xor.ll
@@ -87,7 +87,7 @@ define i32 @selecti64i32(i64 %a) {
; CHECK6M: @ %bb.0:
; CHECK6M-NEXT: ldr r0, .LCPI2_0
; CHECK6M-NEXT: cmp r1, #0
-; CHECK6M-NEXT: bge .LBB2_2
+; CHECK6M-NEXT: bpl .LBB2_2
; CHECK6M-NEXT: @ %bb.1:
; CHECK6M-NEXT: adds r0, r0, #1
; CHECK6M-NEXT: .LBB2_2:
@@ -328,7 +328,7 @@ define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
; CHECK6M-LABEL: icmpasrne:
; CHECK6M: @ %bb.0:
; CHECK6M-NEXT: cmp r0, #0
-; CHECK6M-NEXT: bge .LBB9_2
+; CHECK6M-NEXT: bpl .LBB9_2
; CHECK6M-NEXT: @ %bb.1:
; CHECK6M-NEXT: mov r1, r2
; CHECK6M-NEXT: .LBB9_2:
diff --git a/llvm/test/CodeGen/Thumb/smul_fix_sat.ll b/llvm/test/CodeGen/Thumb/smul_fix_sat.ll
index 24209b45e302d..210c286e7bdb8 100644
--- a/llvm/test/CodeGen/Thumb/smul_fix_sat.ll
+++ b/llvm/test/CodeGen/Thumb/smul_fix_sat.ll
@@ -429,7 +429,7 @@ define i64 @func7(i64 %x, i64 %y) nounwind {
; ARM-NEXT: str r0, [sp, #16] @ 4-byte Spill
; ARM-NEXT: cmp r0, #0
; ARM-NEXT: mov r3, r2
-; ARM-NEXT: bge .LBB6_2
+; ARM-NEXT: bpl .LBB6_2
; ARM-NEXT: @ %bb.1:
; ARM-NEXT: mov r3, r4
; ARM-NEXT: .LBB6_2:
``````````
</details>
https://github.com/llvm/llvm-project/pull/150781
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