[llvm] [NVPTX] Enhance `mul.wide` and `mad.wide` peepholes (PR #150477)

[Alex MacLean via llvm-commits]

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@@ -5408,6 +5408,53 @@ static SDValue PerformREMCombine(SDNode *N,
   return SDValue();
 }
 
+// (any_extend|sign_extend|zero_extend (mul|shl) x, y) -> (mul.wide x, y)
+static SDValue
+PerformExtendMULWIDECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
+  unsigned ExtOpcode = N->getOpcode();
+  assert(ExtOpcode == ISD::ANY_EXTEND || ExtOpcode == ISD::SIGN_EXTEND ||
+         ExtOpcode == ISD::ZERO_EXTEND);
+  EVT ToVT = N->getValueType(0);
+  if (!(ToVT == MVT::i32 || ToVT == MVT::i64))
+    return SDValue();
+  SDValue Op = N->getOperand(0);
+  if (!(Op.getOpcode() == ISD::MUL || Op.getOpcode() == ISD::SHL))
+    return SDValue();
+  if (Op.getOpcode() == ISD::SHL && !isa<ConstantSDNode>(Op.getOperand(1)))
+    return SDValue();
+  EVT FromVT = Op.getValueType();
+  if (!(FromVT == MVT::i16 || FromVT == MVT::i32))
----------------
AlexMaclean wrote:

What if the ext is from i16 to i64? Will we emit an un-lowerable MUL_WIDE node here? Please add some test cases for this case. 

https://github.com/llvm/llvm-project/pull/150477