[llvm] [RISCV] Rewrite deinterleave load as vlse optimization as DAG combine (PR #150049)

[Philip Reames via llvm-commits]

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@@ -16,8 +16,10 @@ define <8 x i8> @load_factor2(ptr %ptr) {
 define <8 x i8> @load_factor3(ptr %ptr) {
 ; CHECK-LABEL: load_factor3:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, a0, 2
+; CHECK-NEXT:    li a1, 3
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT:    vlseg3e8.v v6, (a0)
+; CHECK-NEXT:    vlse8.v v8, (a0), a1
 ; CHECK-NEXT:    ret
     %1 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg3.load.mask.v8i8.i64(ptr %ptr, <8 x i1> splat (i1 true), i64 8)
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preames wrote:

Yep, I plan to go through and do this now that the basic design seems to be on a path to acceptance.  (I'd mentioned this in the description.)

https://github.com/llvm/llvm-project/pull/150049