[llvm] [RISCV] Rewrite deinterleave load as vlse optimization as DAG combine (PR #150049)

[Min-Yih Hsu via llvm-commits]

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@@ -182,8 +182,10 @@ entry:
 define <vscale x 1 x i8> @test_vlseg3_mask_nxv1i8_triscv.vector.tuple_nxv1i8_3t(ptr %base, i32 %vl, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: test_vlseg3_mask_nxv1i8_triscv.vector.tuple_nxv1i8_3t:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    li a2, 3
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT:    vlseg3e8.v v7, (a0), v0.t
+; CHECK-NEXT:    vlse8.v v8, (a0), a2, v0.t
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mshockwave wrote:

ditto test coverage

https://github.com/llvm/llvm-project/pull/150049