[llvm] [RISCV] Rewrite deinterleave load as vlse optimization as DAG combine (PR #150049)

[Min-Yih Hsu via llvm-commits]

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@@ -20764,6 +20764,54 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
     }
     break;
   }
+  case RISCVISD::TUPLE_EXTRACT: {
+    EVT VT = N->getValueType(0);
+    SDValue Tuple = N->getOperand(0);
+    unsigned Idx = N->getConstantOperandVal(1);
+    if (!Tuple.hasOneUse() || Tuple.getOpcode() != ISD::INTRINSIC_W_CHAIN)
+      break;
+
+    unsigned NF = 0;
+    switch (Tuple.getConstantOperandVal(1)) {
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mshockwave wrote:

non-blocking: I noticed there is a static function `getSegInstNF` in RISCVISelDAGToDAG.cpp that does the same thing, perhaps we can turn it into a shared function.

https://github.com/llvm/llvm-project/pull/150049