[llvm] [RISCV][TTI] Enable masked interleave access for scalable vector (PR #149981)
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 25 08:13:55 PDT 2025
asb wrote:
This patch has caused an assertion on the zvl1024b builder [[1]](https://lab.llvm.org/buildbot/#/builders/213/builds/112) (actually the first zvl-specific failure the recently added builders have caught I think, so good to see the infra paying off):
```
clang-21: ../../llvm/lib/Transforms/Vectorize/LoopVectorize.cpp:7132: VectorizationFactor llvm::LoopVectorizationPlanner::computeBestVF(): Assertion `(BestFactor.Width == LegacyVF.Width || BestPlan.hasEarlyExit() || planContainsAdditionalSimplifications(getPlanFor(BestFactor.Width), CostCtx, OrigLoop, BestFactor.Width) || planContainsAdditionalSimplifications( getPlanFor(LegacyVF.Width), CostCtx, OrigLoop, LegacyVF.Width)) && " VPlan cost model and legacy cost model disagreed"' failed.
```
I'm reverting it now so the issue can be resolved without undue time pressure, but this minimised test case should help:
```
cat - <<'EOF' > reduced.ll
; ModuleID = '<stdin>'
source_filename = "<stdin>"
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
target triple = "riscv64-unknown-linux-gnu"
define ptr @ham(ptr %arg) {
bb:
store ptr null, ptr %arg, align 8
ret ptr null
}
define ptr @zot(i64 %arg) {
bb:
br label %bb1
bb1: ; preds = %bb4, %bb
%phi = phi ptr [ null, %bb ], [ %getelementptr, %bb4 ]
%phi2 = phi i64 [ %arg, %bb ], [ %add, %bb4 ]
%icmp = icmp sgt i64 %phi2, 0
br i1 %icmp, label %bb4, label %bb3
bb3: ; preds = %bb1
ret ptr null
bb4: ; preds = %bb1
%call = call ptr @ham(ptr %phi)
%getelementptr = getelementptr nusw i8, ptr %phi, i64 16
%add = add i64 %phi2, -1
br label %bb1
}
EOF
./build/rvrel/bin/clang++ --target=riscv64-linux-gnu -march=rva23u64_zvl1024b -O3 reduced.ll
```
https://github.com/llvm/llvm-project/pull/149981
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