[llvm] [RISCV] Remove fixed vector constraint on masked interleave costing (PR #150624)

Philip Reames via llvm-commits llvm-commits at lists.llvm.org
Fri Jul 25 07:25:37 PDT 2025


https://github.com/preames created https://github.com/llvm/llvm-project/pull/150624

The last of the fixed vector changes for interleaves with masked loads and stores landed last night, so we no longer need the restriction.

Note that our costing in LV will nearly always prefer a scalable type, so this is pretty invisible in practice.  All the lowering paths are tested directly.  

>From 8bf619a95fed0e1c0ae152cc2d447cc4aa151dc6 Mon Sep 17 00:00:00 2001
From: Philip Reames <preames at rivosinc.com>
Date: Fri, 25 Jul 2025 07:15:44 -0700
Subject: [PATCH] [RISCV] Remove fixed vector constraint on masked interleave
 costing

The last of the fixed vector changes for interleaves with masked
loads and stores landed last night, so we no longer need the
restriction.
---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 1624f12a102e3..4899cfdc04fd0 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -983,9 +983,7 @@ InstructionCost RISCVTTIImpl::getInterleavedMemoryOpCost(
   // with an adjacent appropriate memory to vlseg/vsseg intrinsics. vlseg/vsseg
   // only support masking per-iteration (i.e. condition), not per-segment (i.e.
   // gap).
-  // TODO: Support masked interleaved access for fixed length vector.
-  if ((isa<ScalableVectorType>(VecTy) || !UseMaskForCond) && !UseMaskForGaps &&
-      Factor <= TLI->getMaxSupportedInterleaveFactor()) {
+  if (!UseMaskForGaps && Factor <= TLI->getMaxSupportedInterleaveFactor()) {
     auto *VTy = cast<VectorType>(VecTy);
     std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(VTy);
     // Need to make sure type has't been scalarized



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