[llvm] [AArch64] Keep floating-point conversion in SIMD (PR #147707)

[Guy David via llvm-commits]

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@@ -24026,6 +24026,63 @@ static SDValue combineBoolVectorAndTruncateStore(SelectionDAG &DAG,
                       Store->getMemOperand());
 }
 
+// Combine store (fp_to_int X) with optional extensions/trunctions to use vector
+// semantics when NEON is available.
+static void combineFPToIntStore(StoreSDNode *ST,
+                                TargetLowering::DAGCombinerInfo &DCI,
+                                SelectionDAG &DAG,
+                                const AArch64Subtarget *Subtarget) {
+  if (!Subtarget->isNeonAvailable())
+    return;
+
+  SDValue Value = ST->getValue();
+  // Peel extensions, truncations and assertions.
+  for (;;) {
+    if (!Value->hasOneUse())
+      break;
+    if (!ISD::isExtOpcode(Value.getOpcode()) &&
----------------
guy-david wrote:

It wasn't, removed. Moved the combine to post-legalization.
Looking through assertions is still necessary, the IR input I was originally interested in optimizing has `AssertZext` on the value being stored.

https://github.com/llvm/llvm-project/pull/147707