[llvm] [AArch64] Keep floating-point conversion in SIMD (PR #147707)

[Paul Walker via llvm-commits]

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@@ -24026,6 +24026,63 @@ static SDValue combineBoolVectorAndTruncateStore(SelectionDAG &DAG,
                       Store->getMemOperand());
 }
 
+// Combine store (fp_to_int X) with optional extensions/trunctions to use vector
+// semantics when NEON is available.
+static void combineFPToIntStore(StoreSDNode *ST,
+                                TargetLowering::DAGCombinerInfo &DCI,
+                                SelectionDAG &DAG,
+                                const AArch64Subtarget *Subtarget) {
+  if (!Subtarget->isNeonAvailable())
+    return;
+
+  SDValue Value = ST->getValue();
+  // Peel extensions, truncations and assertions.
+  for (;;) {
+    if (!Value->hasOneUse())
+      break;
+    if (!ISD::isExtOpcode(Value.getOpcode()) &&
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paulwalker-arm wrote:

How important is it to peel extensions? I ask because the remaining code doesn't look resilient to them.  The final bitcast will likely mean "extra" bits contain junk.  To me it looks like you only care about truncation?

Related to this, the store itself could be a truncating store?  I think it's worth restricting the combine until after legalisation (especially as the goal is to modify the dag to make it more amenable to selection). That way things would have settled down and my guess is the combine will see a truncating store and so there will be nothing to peel.

https://github.com/llvm/llvm-project/pull/147707