[llvm] [AArch64] Keep floating-point conversion in SIMD (PR #147707)

[Paul Walker via llvm-commits]

================
@@ -24026,6 +24026,63 @@ static SDValue combineBoolVectorAndTruncateStore(SelectionDAG &DAG,
                       Store->getMemOperand());
 }
 
+// Combine store (fp_to_int X) with optional extensions/trunctions to use vector
+// semantics when NEON is available.
+static void combineFPToIntStore(StoreSDNode *ST,
+                                TargetLowering::DAGCombinerInfo &DCI,
+                                SelectionDAG &DAG,
+                                const AArch64Subtarget *Subtarget) {
+  if (!Subtarget->isNeonAvailable())
+    return;
+
+  SDValue Value = ST->getValue();
+  // Peel extensions, truncations and assertions.
+  for (;;) {
+    if (!Value->hasOneUse())
+      break;
+    if (!ISD::isExtOpcode(Value.getOpcode()) &&
+        Value.getOpcode() != ISD::TRUNCATE && !Value->isAssert())
+      break;
+    Value = Value.getOperand(0);
+  }
+
+  if (Value.getOpcode() != ISD::FP_TO_UINT &&
+      Value.getOpcode() != ISD::FP_TO_SINT)
+    return;
+  if (!Value.hasOneUse())
+    return;
+
+  SDValue FPSrc = Value.getOperand(0);
+  EVT SrcVT = FPSrc.getValueType();
+  if (SrcVT.isVector())
+    return;
+
+  // Create a two-element vector to avoid widening. The floating point
+  // conversion is transformed into a single element conversion via a pattern.
+  EVT VecSrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, 2);
+  EVT DstVT = MVT::getIntegerVT(SrcVT.getScalarSizeInBits());
+  EVT VecDstVT = EVT::getVectorVT(*DAG.getContext(), DstVT, 2);
+  SDLoc DL(ST);
+  SDValue UndefVec = DAG.getUNDEF(VecSrcVT);
+  SDValue Zero = DAG.getConstant(0, DL, MVT::i64);
----------------
paulwalker-arm wrote:

```suggestion
  SDValue Zero = DAG.getVectorIdxConstant(0, DL);
```

https://github.com/llvm/llvm-project/pull/147707