[llvm] [GVN][Tests] Add MSSA coverage to some PRE tests (PR #150603)
Madhur Amilkanthwar via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 25 03:37:56 PDT 2025
https://github.com/madhur13490 created https://github.com/llvm/llvm-project/pull/150603
None
>From f807237924f559ddbceb47e600d6ab1949add307 Mon Sep 17 00:00:00 2001
From: Madhur Amilkanthwar <madhura at nvidia.com>
Date: Fri, 25 Jul 2025 02:47:20 -0700
Subject: [PATCH] [GVN][Tests] Add MSSA coverage to some PRE tests
---
llvm/test/Transforms/GVN/PRE/load-metadata.ll | 47 +-
.../GVN/PRE/load-pre-across-backedge.ll | 6 +-
.../Transforms/GVN/PRE/load-pre-nonlocal.ll | 6 +-
.../GVN/PRE/load-pre-split-backedge.ll | 41 +-
.../test/Transforms/GVN/PRE/lpre-call-wrap.ll | 80 +-
.../Transforms/GVN/PRE/rle-addrspace-cast.ll | 24 +-
.../Transforms/GVN/PRE/rle-semidominated.ll | 55 +-
llvm/test/Transforms/GVN/PRE/rle.ll | 1095 +++++++++--------
8 files changed, 764 insertions(+), 590 deletions(-)
diff --git a/llvm/test/Transforms/GVN/PRE/load-metadata.ll b/llvm/test/Transforms/GVN/PRE/load-metadata.ll
index 415812be95b3a..1128b1be199c2 100644
--- a/llvm/test/Transforms/GVN/PRE/load-metadata.ll
+++ b/llvm/test/Transforms/GVN/PRE/load-metadata.ll
@@ -1,14 +1,40 @@
-; RUN: opt -S -passes=gvn < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -S -passes=gvn < %s | FileCheck %s --check-prefixes=CHECK,MDEP
+; RUN: opt -S -passes='gvn<memoryssa>' < %s | FileCheck %s --check-prefixes=CHECK,MSSA
define i32 @test1(ptr %p, i1 %C) {
-; CHECK-LABEL: @test1(
+; MDEP-LABEL: define i32 @test1(
+; MDEP-SAME: ptr [[P:%.*]], i1 [[C:%.*]]) {
+; MDEP-NEXT: [[BLOCK1:.*:]]
+; MDEP-NEXT: br i1 [[C]], label %[[BLOCK2:.*]], label %[[BLOCK3:.*]]
+; MDEP: [[BLOCK2]]:
+; MDEP-NEXT: [[PRE_PRE:%.*]] = load i32, ptr [[P]], align 4, !range [[RNG0:![0-9]+]], !invariant.group [[META1:![0-9]+]]
+; MDEP-NEXT: br label %[[BLOCK4:.*]]
+; MDEP: [[BLOCK3]]:
+; MDEP-NEXT: store i32 0, ptr [[P]], align 4
+; MDEP-NEXT: br label %[[BLOCK4]]
+; MDEP: [[BLOCK4]]:
+; MDEP-NEXT: [[PRE:%.*]] = phi i32 [ 0, %[[BLOCK3]] ], [ [[PRE_PRE]], %[[BLOCK2]] ]
+; MDEP-NEXT: ret i32 [[PRE]]
+;
+; MSSA-LABEL: define i32 @test1(
+; MSSA-SAME: ptr [[P:%.*]], i1 [[C:%.*]]) {
+; MSSA-NEXT: [[BLOCK1:.*:]]
+; MSSA-NEXT: br i1 [[C]], label %[[BLOCK2:.*]], label %[[BLOCK3:.*]]
+; MSSA: [[BLOCK2]]:
+; MSSA-NEXT: br label %[[BLOCK4:.*]]
+; MSSA: [[BLOCK3]]:
+; MSSA-NEXT: store i32 0, ptr [[P]], align 4
+; MSSA-NEXT: br label %[[BLOCK4]]
+; MSSA: [[BLOCK4]]:
+; MSSA-NEXT: [[PRE:%.*]] = load i32, ptr [[P]], align 4, !range [[RNG0:![0-9]+]], !invariant.group [[META1:![0-9]+]]
+; MSSA-NEXT: ret i32 [[PRE]]
+;
block1:
- br i1 %C, label %block2, label %block3
+ br i1 %C, label %block2, label %block3
block2:
- br label %block4
-; CHECK: block2:
-; CHECK-NEXT: load i32, ptr %p, align 4, !range !0, !invariant.group !1
+ br label %block4
block3:
store i32 0, ptr %p
@@ -22,3 +48,12 @@ block4:
!0 = !{i32 40, i32 100}
!1 = !{!"magic ptr"}
+;.
+; MDEP: [[RNG0]] = !{i32 40, i32 100}
+; MDEP: [[META1]] = !{!"magic ptr"}
+;.
+; MSSA: [[RNG0]] = !{i32 40, i32 100}
+; MSSA: [[META1]] = !{!"magic ptr"}
+;.
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/Transforms/GVN/PRE/load-pre-across-backedge.ll b/llvm/test/Transforms/GVN/PRE/load-pre-across-backedge.ll
index a3eae62ff6dc3..b6772725d2a88 100644
--- a/llvm/test/Transforms/GVN/PRE/load-pre-across-backedge.ll
+++ b/llvm/test/Transforms/GVN/PRE/load-pre-across-backedge.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=gvn -S < %s | FileCheck %s
+; RUN: opt -passes=gvn -S < %s | FileCheck %s --check-prefixes=CHECK,MDEP
+; RUN: opt -passes='gvn<memoryssa>' -S < %s | FileCheck %s --check-prefixes=CHECK,MSSA
; Check that PRE-LOAD across backedge does not
; result in invalid dominator tree.
@@ -43,3 +44,6 @@ bb3:
call void @use(i32 %v)
br label %bb2
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; MDEP: {{.*}}
+; MSSA: {{.*}}
diff --git a/llvm/test/Transforms/GVN/PRE/load-pre-nonlocal.ll b/llvm/test/Transforms/GVN/PRE/load-pre-nonlocal.ll
index b778d985ff418..9dba73a1beb77 100644
--- a/llvm/test/Transforms/GVN/PRE/load-pre-nonlocal.ll
+++ b/llvm/test/Transforms/GVN/PRE/load-pre-nonlocal.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -o - -passes=gvn %s | FileCheck %s
+; RUN: opt -S -o - -passes=gvn %s | FileCheck %s --check-prefixes=CHECK,MDEP
+; RUN: opt -S -o - -passes='gvn<memoryssa>' %s | FileCheck %s --check-prefixes=CHECK,MSSA
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
@@ -143,3 +144,6 @@ if.end:
file: !12,
isOptimized: true, flags: "-O2",
splitDebugFilename: "abc.debug", emissionKind: 2)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; MDEP: {{.*}}
+; MSSA: {{.*}}
diff --git a/llvm/test/Transforms/GVN/PRE/load-pre-split-backedge.ll b/llvm/test/Transforms/GVN/PRE/load-pre-split-backedge.ll
index 5f9fbc36b6521..9b4e6b415db76 100644
--- a/llvm/test/Transforms/GVN/PRE/load-pre-split-backedge.ll
+++ b/llvm/test/Transforms/GVN/PRE/load-pre-split-backedge.ll
@@ -1,27 +1,26 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -passes=gvn -enable-split-backedge-in-load-pre=true < %s | FileCheck %s --check-prefix=ON
-; RUN: opt -S -passes=gvn -enable-split-backedge-in-load-pre=false < %s | FileCheck %s --check-prefix=OFF
+; RUN: opt -S -passes=gvn -enable-split-backedge-in-load-pre=true < %s | FileCheck %s --check-prefix=ON --check-prefixes=CHECK,MDEP
+; RUN: opt -S -passes='gvn<memoryssa>' -enable-split-backedge-in-load-pre=true < %s | FileCheck %s --check-prefix=ON --check-prefixes=CHECK,MSSA
+; RUN: opt -S -passes=gvn -enable-split-backedge-in-load-pre=false < %s | FileCheck %s --check-prefix=OFF --check-prefixes=CHECK,MDEP
+; RUN: opt -S -passes='gvn<memoryssa>' -enable-split-backedge-in-load-pre=false < %s | FileCheck %s --check-prefix=OFF --check-prefixes=CHECK,MSSA
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
define i32 @test(i1 %b, i1 %c, ptr noalias %p, ptr noalias %q) {
-; ON-LABEL: @test(
-; ON-NEXT: entry:
-; ON-NEXT: [[Y1:%.*]] = load i32, ptr [[P:%.*]], align 4
-; ON-NEXT: call void @use(i32 [[Y1]])
-; ON-NEXT: br label [[HEADER:%.*]]
-; ON: header:
-; ON-NEXT: [[Y:%.*]] = phi i32 [ [[Y_PRE:%.*]], [[SKIP_HEADER_CRIT_EDGE:%.*]] ], [ [[Y]], [[HEADER]] ], [ [[Y1]], [[ENTRY:%.*]] ]
-; ON-NEXT: call void @use(i32 [[Y]])
-; ON-NEXT: br i1 [[B:%.*]], label [[SKIP:%.*]], label [[HEADER]]
-; ON: skip:
-; ON-NEXT: call void @clobber(ptr [[P]], ptr [[Q:%.*]])
-; ON-NEXT: br i1 [[C:%.*]], label [[SKIP_HEADER_CRIT_EDGE]], label [[EXIT:%.*]]
-; ON: skip.header_crit_edge:
-; ON-NEXT: [[Y_PRE]] = load i32, ptr [[P]], align 4
-; ON-NEXT: br label [[HEADER]]
-; ON: exit:
-; ON-NEXT: ret i32 [[Y]]
+; MSSA-LABEL: @test(
+; MSSA-NEXT: entry:
+; MSSA-NEXT: [[Y1:%.*]] = load i32, ptr [[P:%.*]], align 4
+; MSSA-NEXT: call void @use(i32 [[Y1]])
+; MSSA-NEXT: br label [[HEADER:%.*]]
+; MSSA: header:
+; MSSA-NEXT: [[Y:%.*]] = load i32, ptr [[P]], align 4
+; MSSA-NEXT: call void @use(i32 [[Y]])
+; MSSA-NEXT: br i1 [[B:%.*]], label [[SKIP:%.*]], label [[HEADER]]
+; MSSA: skip:
+; MSSA-NEXT: call void @clobber(ptr [[P]], ptr [[Q:%.*]])
+; MSSA-NEXT: br i1 [[C:%.*]], label [[HEADER]], label [[EXIT:%.*]]
+; MSSA: exit:
+; MSSA-NEXT: ret i32 [[Y]]
;
; OFF-LABEL: @test(
; OFF-NEXT: entry:
@@ -55,3 +54,7 @@ exit:
declare void @use(i32) readonly
declare void @clobber(ptr %p, ptr %q)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
+; MDEP: {{.*}}
+; ON: {{.*}}
diff --git a/llvm/test/Transforms/GVN/PRE/lpre-call-wrap.ll b/llvm/test/Transforms/GVN/PRE/lpre-call-wrap.ll
index 06a7f11aff14b..9b4eb6097ebb0 100644
--- a/llvm/test/Transforms/GVN/PRE/lpre-call-wrap.ll
+++ b/llvm/test/Transforms/GVN/PRE/lpre-call-wrap.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -passes=gvn -enable-load-pre < %s | FileCheck %s
+; RUN: opt -S -passes=gvn -enable-load-pre < %s | FileCheck %s --check-prefixes=CHECK,MDEP
+; RUN: opt -S -passes='gvn<memoryssa>' -enable-load-pre < %s | FileCheck %s --check-prefixes=CHECK,MSSA
;
; Make sure the load in bb3.backedge is removed and moved into bb1 after the
; call. This makes the non-call case faster.
@@ -18,31 +19,56 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
%struct.A = type { i32, i32 }
define void @_Z12testfunctionR1A(ptr %iter) {
-; CHECK-LABEL: @_Z12testfunctionR1A(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ITER:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 0
-; CHECK-NEXT: br i1 [[TMP1]], label [[RETURN:%.*]], label [[BB_NPH:%.*]]
-; CHECK: bb.nph:
-; CHECK-NEXT: [[TMP2:%.*]] = getelementptr [[STRUCT_A:%.*]], ptr [[ITER]], i32 0, i32 1
-; CHECK-NEXT: br label [[BB:%.*]]
-; CHECK: bb:
-; CHECK-NEXT: [[DOTRLE:%.*]] = phi i32 [ [[TMP0]], [[BB_NPH]] ], [ [[TMP6:%.*]], [[BB3_BACKEDGE:%.*]] ]
-; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[DOTRLE]], 1
-; CHECK-NEXT: store i32 [[TMP3]], ptr [[ITER]], align 4
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP2]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP3]], [[TMP4]]
-; CHECK-NEXT: br i1 [[TMP5]], label [[BB1:%.*]], label [[BB3_BACKEDGE]]
-; CHECK: bb1:
-; CHECK-NEXT: tail call void @_Z1gv()
-; CHECK-NEXT: [[DOTPRE:%.*]] = load i32, ptr [[ITER]], align 4
-; CHECK-NEXT: br label [[BB3_BACKEDGE]]
-; CHECK: bb3.backedge:
-; CHECK-NEXT: [[TMP6]] = phi i32 [ [[DOTPRE]], [[BB1]] ], [ [[TMP3]], [[BB]] ]
-; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
-; CHECK-NEXT: br i1 [[TMP7]], label [[RETURN]], label [[BB]]
-; CHECK: return:
-; CHECK-NEXT: ret void
+; MDEP-LABEL: @_Z12testfunctionR1A(
+; MDEP-NEXT: entry:
+; MDEP-NEXT: [[TMP0:%.*]] = load i32, ptr [[ITER:%.*]], align 4
+; MDEP-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 0
+; MDEP-NEXT: br i1 [[TMP1]], label [[RETURN:%.*]], label [[BB_NPH:%.*]]
+; MDEP: bb.nph:
+; MDEP-NEXT: [[TMP2:%.*]] = getelementptr [[STRUCT_A:%.*]], ptr [[ITER]], i32 0, i32 1
+; MDEP-NEXT: br label [[BB:%.*]]
+; MDEP: bb:
+; MDEP-NEXT: [[DOTRLE:%.*]] = phi i32 [ [[TMP0]], [[BB_NPH]] ], [ [[TMP6:%.*]], [[BB3_BACKEDGE:%.*]] ]
+; MDEP-NEXT: [[TMP3:%.*]] = add i32 [[DOTRLE]], 1
+; MDEP-NEXT: store i32 [[TMP3]], ptr [[ITER]], align 4
+; MDEP-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP2]], align 4
+; MDEP-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP3]], [[TMP4]]
+; MDEP-NEXT: br i1 [[TMP5]], label [[BB1:%.*]], label [[BB3_BACKEDGE]]
+; MDEP: bb1:
+; MDEP-NEXT: tail call void @_Z1gv()
+; MDEP-NEXT: [[DOTPRE:%.*]] = load i32, ptr [[ITER]], align 4
+; MDEP-NEXT: br label [[BB3_BACKEDGE]]
+; MDEP: bb3.backedge:
+; MDEP-NEXT: [[TMP6]] = phi i32 [ [[DOTPRE]], [[BB1]] ], [ [[TMP3]], [[BB]] ]
+; MDEP-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
+; MDEP-NEXT: br i1 [[TMP7]], label [[RETURN]], label [[BB]]
+; MDEP: return:
+; MDEP-NEXT: ret void
+;
+; MSSA-LABEL: @_Z12testfunctionR1A(
+; MSSA-NEXT: entry:
+; MSSA-NEXT: [[TMP0:%.*]] = load i32, ptr [[ITER:%.*]], align 4
+; MSSA-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 0
+; MSSA-NEXT: br i1 [[TMP1]], label [[RETURN:%.*]], label [[BB_NPH:%.*]]
+; MSSA: bb.nph:
+; MSSA-NEXT: [[TMP2:%.*]] = getelementptr [[STRUCT_A:%.*]], ptr [[ITER]], i32 0, i32 1
+; MSSA-NEXT: br label [[BB:%.*]]
+; MSSA: bb:
+; MSSA-NEXT: [[DOTRLE:%.*]] = phi i32 [ [[TMP0]], [[BB_NPH]] ], [ [[TMP6:%.*]], [[BB3_BACKEDGE:%.*]] ]
+; MSSA-NEXT: [[TMP3:%.*]] = add i32 [[DOTRLE]], 1
+; MSSA-NEXT: store i32 [[TMP3]], ptr [[ITER]], align 4
+; MSSA-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP2]], align 4
+; MSSA-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP3]], [[TMP4]]
+; MSSA-NEXT: br i1 [[TMP5]], label [[BB1:%.*]], label [[BB3_BACKEDGE]]
+; MSSA: bb1:
+; MSSA-NEXT: tail call void @_Z1gv()
+; MSSA-NEXT: br label [[BB3_BACKEDGE]]
+; MSSA: bb3.backedge:
+; MSSA-NEXT: [[TMP6]] = load i32, ptr [[ITER]], align 4
+; MSSA-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
+; MSSA-NEXT: br i1 [[TMP7]], label [[RETURN]], label [[BB]]
+; MSSA: return:
+; MSSA-NEXT: ret void
;
entry:
%0 = getelementptr %struct.A, ptr %iter, i32 0, i32 0 ; <ptr> [#uses=3]
@@ -76,3 +102,5 @@ return: ; preds = %bb3.backedge, %entry
}
declare void @_Z1gv()
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/Transforms/GVN/PRE/rle-addrspace-cast.ll b/llvm/test/Transforms/GVN/PRE/rle-addrspace-cast.ll
index 7f67b2b13647d..6c79b02efbd24 100644
--- a/llvm/test/Transforms/GVN/PRE/rle-addrspace-cast.ll
+++ b/llvm/test/Transforms/GVN/PRE/rle-addrspace-cast.ll
@@ -1,6 +1,23 @@
-; RUN: opt < %s -data-layout="e-p:32:32:32-p1:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-n8:16:32" -passes=gvn,dce -S | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt < %s -data-layout="e-p:32:32:32-p1:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-n8:16:32" -passes=gvn,dce -S | FileCheck %s --check-prefixes=CHECK,MDEP
+; RUN: opt < %s -data-layout="e-p:32:32:32-p1:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-n8:16:32" -passes='gvn<memoryssa>',dce -S | FileCheck %s --check-prefixes=CHECK,MSSA
define i8 @coerce_offset0_addrspacecast(i32 %V, ptr %P) {
+; MDEP-LABEL: define i8 @coerce_offset0_addrspacecast(
+; MDEP-SAME: i32 [[V:%.*]], ptr [[P:%.*]]) {
+; MDEP-NEXT: store i32 [[V]], ptr [[P]], align 4
+; MDEP-NEXT: [[TMP1:%.*]] = lshr i32 [[V]], 16
+; MDEP-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
+; MDEP-NEXT: ret i8 [[TMP2]]
+;
+; MSSA-LABEL: define i8 @coerce_offset0_addrspacecast(
+; MSSA-SAME: i32 [[V:%.*]], ptr [[P:%.*]]) {
+; MSSA-NEXT: store i32 [[V]], ptr [[P]], align 4
+; MSSA-NEXT: [[P2:%.*]] = addrspacecast ptr [[P]] to ptr addrspace(1)
+; MSSA-NEXT: [[P3:%.*]] = getelementptr i8, ptr addrspace(1) [[P2]], i32 2
+; MSSA-NEXT: [[A:%.*]] = load i8, ptr addrspace(1) [[P3]], align 1
+; MSSA-NEXT: ret i8 [[A]]
+;
store i32 %V, ptr %P
%P2 = addrspacecast ptr %P to ptr addrspace(1)
@@ -8,7 +25,6 @@ define i8 @coerce_offset0_addrspacecast(i32 %V, ptr %P) {
%A = load i8, ptr addrspace(1) %P3
ret i8 %A
-; CHECK-LABEL: @coerce_offset0_addrspacecast(
-; CHECK-NOT: load
-; CHECK: ret i8
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/Transforms/GVN/PRE/rle-semidominated.ll b/llvm/test/Transforms/GVN/PRE/rle-semidominated.ll
index e927f37cb0101..4eb090e18110e 100644
--- a/llvm/test/Transforms/GVN/PRE/rle-semidominated.ll
+++ b/llvm/test/Transforms/GVN/PRE/rle-semidominated.ll
@@ -1,13 +1,45 @@
-; RUN: opt < %s -passes=gvn -S | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt < %s -passes=gvn -S | FileCheck %s --check-prefixes=CHECK,MDEP
+; RUN: opt < %s -passes='gvn<memoryssa>' -S | FileCheck %s --check-prefixes=CHECK,MSSA
define i32 @main(ptr %p, i32 %x, i32 %y) {
+; MDEP-LABEL: define i32 @main(
+; MDEP-SAME: ptr [[P:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]]) {
+; MDEP-NEXT: [[BLOCK1:.*:]]
+; MDEP-NEXT: [[CMP:%.*]] = icmp eq i32 [[X]], [[Y]]
+; MDEP-NEXT: br i1 [[CMP]], label %[[BLOCK2:.*]], label %[[BLOCK3:.*]]
+; MDEP: [[BLOCK2]]:
+; MDEP-NEXT: [[DEAD_PRE:%.*]] = load i32, ptr [[P]], align 4
+; MDEP-NEXT: br label %[[BLOCK4:.*]]
+; MDEP: [[BLOCK3]]:
+; MDEP-NEXT: store i32 0, ptr [[P]], align 4
+; MDEP-NEXT: br label %[[BLOCK4]]
+; MDEP: [[BLOCK4]]:
+; MDEP-NEXT: [[DEAD:%.*]] = phi i32 [ 0, %[[BLOCK3]] ], [ [[DEAD_PRE]], %[[BLOCK2]] ]
+; MDEP-NEXT: ret i32 [[DEAD]]
+;
+; MSSA-LABEL: define i32 @main(
+; MSSA-SAME: ptr [[P:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]]) {
+; MSSA-NEXT: [[BLOCK1:.*:]]
+; MSSA-NEXT: [[Z:%.*]] = load i32, ptr [[P]], align 4
+; MSSA-NEXT: [[CMP:%.*]] = icmp eq i32 [[X]], [[Y]]
+; MSSA-NEXT: br i1 [[CMP]], label %[[BLOCK2:.*]], label %[[BLOCK3:.*]]
+; MSSA: [[BLOCK2]]:
+; MSSA-NEXT: br label %[[BLOCK4:.*]]
+; MSSA: [[BLOCK3]]:
+; MSSA-NEXT: store i32 0, ptr [[P]], align 4
+; MSSA-NEXT: br label %[[BLOCK4]]
+; MSSA: [[BLOCK4]]:
+; MSSA-NEXT: [[DEAD:%.*]] = load i32, ptr [[P]], align 4
+; MSSA-NEXT: ret i32 [[DEAD]]
+;
block1:
%z = load i32, ptr %p
%cmp = icmp eq i32 %x, %y
- br i1 %cmp, label %block2, label %block3
+ br i1 %cmp, label %block2, label %block3
block2:
- br label %block4
+ br label %block4
block3:
%b = bitcast i32 0 to i32
@@ -19,18 +51,5 @@ block4:
ret i32 %DEAD
}
-; CHECK: define i32 @main(ptr %p, i32 %x, i32 %y) {
-; CHECK-NEXT: block1:
-; CHECK-NOT: %z = load i32, ptr %p
-; CHECK-NEXT: %cmp = icmp eq i32 %x, %y
-; CHECK-NEXT: br i1 %cmp, label %block2, label %block3
-; CHECK: block2:
-; CHECK-NEXT: %DEAD.pre = load i32, ptr %p
-; CHECK-NEXT: br label %block4
-; CHECK: block3:
-; CHECK-NEXT: store i32 0, ptr %p
-; CHECK-NEXT: br label %block4
-; CHECK: block4:
-; CHECK-NEXT: %DEAD = phi i32 [ 0, %block3 ], [ %DEAD.pre, %block2 ]
-; CHECK-NEXT: ret i32 %DEAD
-; CHECK-NEXT: }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/Transforms/GVN/PRE/rle.ll b/llvm/test/Transforms/GVN/PRE/rle.ll
index c81c1fe1c982f..4abf70d3fe01c 100644
--- a/llvm/test/Transforms/GVN/PRE/rle.ll
+++ b/llvm/test/Transforms/GVN/PRE/rle.ll
@@ -1,12 +1,19 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -data-layout="e-p:32:32:32-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-n8:16:32" -passes=gvn,dce -enable-split-backedge-in-load-pre -S | FileCheck %s --check-prefixes=CHECK,LE
-; RUN: opt < %s -data-layout="E-p:32:32:32-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-n32" -passes=gvn,dce -enable-split-backedge-in-load-pre -S | FileCheck %s --check-prefixes=CHECK,BE
+; RUN: opt < %s -data-layout="e-p:32:32:32-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-n8:16:32" -passes=gvn,dce -enable-split-backedge-in-load-pre -S | FileCheck %s --check-prefixes=CHECK,LE --check-prefixes=CHECK,MDEP
+; RUN: opt < %s -data-layout="e-p:32:32:32-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-n8:16:32" -passes='gvn<memoryssa>',dce -enable-split-backedge-in-load-pre -S | FileCheck %s --check-prefixes=CHECK,LE --check-prefixes=CHECK,MSSA
+; RUN: opt < %s -data-layout="E-p:32:32:32-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-n32" -passes=gvn,dce -enable-split-backedge-in-load-pre -S | FileCheck %s --check-prefixes=CHECK,BE --check-prefixes=CHECK,MDEP
+; RUN: opt < %s -data-layout="E-p:32:32:32-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-n32" -passes='gvn<memoryssa>',dce -enable-split-backedge-in-load-pre -S | FileCheck %s --check-prefixes=CHECK,BE --check-prefixes=CHECK,MSSA
;; Trivial RLE test.
define i32 @test0(i32 %V, ptr %P) {
-; CHECK-LABEL: @test0(
-; CHECK-NEXT: store i32 [[V:%.*]], ptr [[P:%.*]], align 4
-; CHECK-NEXT: ret i32 [[V]]
+; MDEP-LABEL: @test0(
+; MDEP-NEXT: store i32 [[V:%.*]], ptr [[P:%.*]], align 4
+; MDEP-NEXT: ret i32 [[V]]
+;
+; MSSA-LABEL: @test0(
+; MSSA-NEXT: store i32 [[V:%.*]], ptr [[P:%.*]], align 4
+; MSSA-NEXT: [[A:%.*]] = load i32, ptr [[P]], align 4
+; MSSA-NEXT: ret i32 [[A]]
;
store i32 %V, ptr %P
@@ -52,10 +59,15 @@ define void @crash1() {
;; i32 -> f32 forwarding.
define float @coerce_mustalias1(i32 %V, ptr %P) {
-; CHECK-LABEL: @coerce_mustalias1(
-; CHECK-NEXT: store i32 [[V:%.*]], ptr [[P:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[V]] to float
-; CHECK-NEXT: ret float [[TMP1]]
+; MDEP-LABEL: @coerce_mustalias1(
+; MDEP-NEXT: store i32 [[V:%.*]], ptr [[P:%.*]], align 4
+; MDEP-NEXT: [[TMP1:%.*]] = bitcast i32 [[V]] to float
+; MDEP-NEXT: ret float [[TMP1]]
+;
+; MSSA-LABEL: @coerce_mustalias1(
+; MSSA-NEXT: store i32 [[V:%.*]], ptr [[P:%.*]], align 4
+; MSSA-NEXT: [[A:%.*]] = load float, ptr [[P]], align 4
+; MSSA-NEXT: ret float [[A]]
;
store i32 %V, ptr %P
@@ -66,11 +78,16 @@ define float @coerce_mustalias1(i32 %V, ptr %P) {
;; ptr -> float forwarding.
define float @coerce_mustalias2(ptr %V, ptr %P) {
-; CHECK-LABEL: @coerce_mustalias2(
-; CHECK-NEXT: store ptr [[V:%.*]], ptr [[P:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[V]] to i32
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[TMP1]] to float
-; CHECK-NEXT: ret float [[TMP2]]
+; MDEP-LABEL: @coerce_mustalias2(
+; MDEP-NEXT: store ptr [[V:%.*]], ptr [[P:%.*]], align 4
+; MDEP-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[V]] to i32
+; MDEP-NEXT: [[TMP2:%.*]] = bitcast i32 [[TMP1]] to float
+; MDEP-NEXT: ret float [[TMP2]]
+;
+; MSSA-LABEL: @coerce_mustalias2(
+; MSSA-NEXT: store ptr [[V:%.*]], ptr [[P:%.*]], align 4
+; MSSA-NEXT: [[A:%.*]] = load float, ptr [[P]], align 4
+; MSSA-NEXT: ret float [[A]]
;
store ptr %V, ptr %P
@@ -81,11 +98,16 @@ define float @coerce_mustalias2(ptr %V, ptr %P) {
;; float -> ptr forwarding.
define ptr @coerce_mustalias3(float %V, ptr %P) {
-; CHECK-LABEL: @coerce_mustalias3(
-; CHECK-NEXT: store float [[V:%.*]], ptr [[P:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[V]] to i32
-; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr
-; CHECK-NEXT: ret ptr [[TMP2]]
+; MDEP-LABEL: @coerce_mustalias3(
+; MDEP-NEXT: store float [[V:%.*]], ptr [[P:%.*]], align 4
+; MDEP-NEXT: [[TMP1:%.*]] = bitcast float [[V]] to i32
+; MDEP-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr
+; MDEP-NEXT: ret ptr [[TMP2]]
+;
+; MSSA-LABEL: @coerce_mustalias3(
+; MSSA-NEXT: store float [[V:%.*]], ptr [[P:%.*]], align 4
+; MSSA-NEXT: [[A:%.*]] = load ptr, ptr [[P]], align 4
+; MSSA-NEXT: ret ptr [[A]]
;
store float %V, ptr %P
@@ -96,14 +118,24 @@ define ptr @coerce_mustalias3(float %V, ptr %P) {
;; i32 -> f32 load forwarding.
define float @coerce_mustalias4(ptr %P, i1 %cond) {
-; CHECK-LABEL: @coerce_mustalias4(
-; CHECK-NEXT: [[A:%.*]] = load i32, ptr [[P:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[A]] to float
-; CHECK-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
-; CHECK: T:
-; CHECK-NEXT: ret float [[TMP1]]
-; CHECK: F:
-; CHECK-NEXT: ret float [[TMP1]]
+; MDEP-LABEL: @coerce_mustalias4(
+; MDEP-NEXT: [[A:%.*]] = load i32, ptr [[P:%.*]], align 4
+; MDEP-NEXT: [[TMP1:%.*]] = bitcast i32 [[A]] to float
+; MDEP-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
+; MDEP: T:
+; MDEP-NEXT: ret float [[TMP1]]
+; MDEP: F:
+; MDEP-NEXT: ret float [[TMP1]]
+;
+; MSSA-LABEL: @coerce_mustalias4(
+; MSSA-NEXT: [[A:%.*]] = load i32, ptr [[P:%.*]], align 4
+; MSSA-NEXT: [[B:%.*]] = load float, ptr [[P]], align 4
+; MSSA-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
+; MSSA: T:
+; MSSA-NEXT: ret float [[B]]
+; MSSA: F:
+; MSSA-NEXT: [[X:%.*]] = bitcast i32 [[A]] to float
+; MSSA-NEXT: ret float [[X]]
;
%A = load i32, ptr %P
@@ -120,16 +152,10 @@ F:
;; i32 -> i8 forwarding
define i8 @coerce_mustalias5(i32 %V, ptr %P) {
-; LE-LABEL: @coerce_mustalias5(
-; LE-NEXT: store i32 [[V:%.*]], ptr [[P:%.*]], align 4
-; LE-NEXT: [[TMP1:%.*]] = trunc i32 [[V]] to i8
-; LE-NEXT: ret i8 [[TMP1]]
-;
-; BE-LABEL: @coerce_mustalias5(
-; BE-NEXT: store i32 [[V:%.*]], ptr [[P:%.*]], align 4
-; BE-NEXT: [[TMP1:%.*]] = lshr i32 [[V]], 24
-; BE-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
-; BE-NEXT: ret i8 [[TMP2]]
+; MSSA-LABEL: @coerce_mustalias5(
+; MSSA-NEXT: store i32 [[V:%.*]], ptr [[P:%.*]], align 4
+; MSSA-NEXT: [[A:%.*]] = load i8, ptr [[P]], align 1
+; MSSA-NEXT: ret i8 [[A]]
;
store i32 %V, ptr %P
@@ -140,18 +166,10 @@ define i8 @coerce_mustalias5(i32 %V, ptr %P) {
;; i64 -> float forwarding
define float @coerce_mustalias6(i64 %V, ptr %P) {
-; LE-LABEL: @coerce_mustalias6(
-; LE-NEXT: store i64 [[V:%.*]], ptr [[P:%.*]], align 4
-; LE-NEXT: [[TMP1:%.*]] = trunc i64 [[V]] to i32
-; LE-NEXT: [[TMP2:%.*]] = bitcast i32 [[TMP1]] to float
-; LE-NEXT: ret float [[TMP2]]
-;
-; BE-LABEL: @coerce_mustalias6(
-; BE-NEXT: store i64 [[V:%.*]], ptr [[P:%.*]], align 4
-; BE-NEXT: [[TMP1:%.*]] = lshr i64 [[V]], 32
-; BE-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32
-; BE-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float
-; BE-NEXT: ret float [[TMP3]]
+; MSSA-LABEL: @coerce_mustalias6(
+; MSSA-NEXT: store i64 [[V:%.*]], ptr [[P:%.*]], align 4
+; MSSA-NEXT: [[A:%.*]] = load float, ptr [[P]], align 4
+; MSSA-NEXT: ret float [[A]]
;
store i64 %V, ptr %P
@@ -162,18 +180,10 @@ define float @coerce_mustalias6(i64 %V, ptr %P) {
;; i64 -> ptr (32-bit) forwarding
define ptr @coerce_mustalias7(i64 %V, ptr %P) {
-; LE-LABEL: @coerce_mustalias7(
-; LE-NEXT: store i64 [[V:%.*]], ptr [[P:%.*]], align 4
-; LE-NEXT: [[TMP1:%.*]] = trunc i64 [[V]] to i32
-; LE-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr
-; LE-NEXT: ret ptr [[TMP2]]
-;
-; BE-LABEL: @coerce_mustalias7(
-; BE-NEXT: store i64 [[V:%.*]], ptr [[P:%.*]], align 4
-; BE-NEXT: [[TMP1:%.*]] = lshr i64 [[V]], 32
-; BE-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32
-; BE-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr
-; BE-NEXT: ret ptr [[TMP3]]
+; MSSA-LABEL: @coerce_mustalias7(
+; MSSA-NEXT: store i64 [[V:%.*]], ptr [[P:%.*]], align 4
+; MSSA-NEXT: [[A:%.*]] = load ptr, ptr [[P]], align 4
+; MSSA-NEXT: ret ptr [[A]]
;
store i64 %V, ptr %P
@@ -184,10 +194,17 @@ define ptr @coerce_mustalias7(i64 %V, ptr %P) {
; memset -> i16 forwarding.
define signext i16 @memset_to_i16_local(ptr %A) nounwind ssp {
-; CHECK-LABEL: @memset_to_i16_local(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: tail call void @llvm.memset.p0.i64(ptr [[A:%.*]], i8 1, i64 200, i1 false)
-; CHECK-NEXT: ret i16 257
+; MDEP-LABEL: @memset_to_i16_local(
+; MDEP-NEXT: entry:
+; MDEP-NEXT: tail call void @llvm.memset.p0.i64(ptr [[A:%.*]], i8 1, i64 200, i1 false)
+; MDEP-NEXT: ret i16 257
+;
+; MSSA-LABEL: @memset_to_i16_local(
+; MSSA-NEXT: entry:
+; MSSA-NEXT: tail call void @llvm.memset.p0.i64(ptr [[A:%.*]], i8 1, i64 200, i1 false)
+; MSSA-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[A]], i64 42
+; MSSA-NEXT: [[TTMP2:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
+; MSSA-NEXT: ret i16 [[TTMP2]]
;
entry:
tail call void @llvm.memset.p0.i64(ptr %A, i8 1, i64 200, i1 false)
@@ -198,16 +215,23 @@ entry:
; memset -> float forwarding.
define float @memset_to_float_local(ptr %A, i8 %Val) nounwind ssp {
-; CHECK-LABEL: @memset_to_float_local(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: tail call void @llvm.memset.p0.i64(ptr [[A:%.*]], i8 [[VAL:%.*]], i64 400, i1 false)
-; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[VAL]] to i32
-; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[TMP0]], 8
-; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP0]], [[TMP1]]
-; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[TMP2]], 16
-; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float
-; CHECK-NEXT: ret float [[TMP5]]
+; MDEP-LABEL: @memset_to_float_local(
+; MDEP-NEXT: entry:
+; MDEP-NEXT: tail call void @llvm.memset.p0.i64(ptr [[A:%.*]], i8 [[VAL:%.*]], i64 400, i1 false)
+; MDEP-NEXT: [[TMP0:%.*]] = zext i8 [[VAL]] to i32
+; MDEP-NEXT: [[TMP1:%.*]] = shl i32 [[TMP0]], 8
+; MDEP-NEXT: [[TMP2:%.*]] = or i32 [[TMP0]], [[TMP1]]
+; MDEP-NEXT: [[TMP3:%.*]] = shl i32 [[TMP2]], 16
+; MDEP-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
+; MDEP-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float
+; MDEP-NEXT: ret float [[TMP5]]
+;
+; MSSA-LABEL: @memset_to_float_local(
+; MSSA-NEXT: entry:
+; MSSA-NEXT: tail call void @llvm.memset.p0.i64(ptr [[A:%.*]], i8 [[VAL:%.*]], i64 400, i1 false)
+; MSSA-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 42
+; MSSA-NEXT: [[TTMP2:%.*]] = load float, ptr [[ARRAYIDX]], align 4
+; MSSA-NEXT: ret float [[TTMP2]]
;
entry:
tail call void @llvm.memset.p0.i64(ptr %A, i8 %Val, i64 400, i1 false)
@@ -218,17 +242,30 @@ entry:
;; non-local memset -> i16 load forwarding.
define i16 @memset_to_i16_nonlocal0(ptr %P, i1 %cond) {
-; CHECK-LABEL: @memset_to_i16_nonlocal0(
-; CHECK-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
-; CHECK: T:
-; CHECK-NEXT: tail call void @llvm.memset.p0.i64(ptr [[P:%.*]], i8 1, i64 400, i1 false)
-; CHECK-NEXT: br label [[CONT:%.*]]
-; CHECK: F:
-; CHECK-NEXT: tail call void @llvm.memset.p0.i64(ptr [[P]], i8 2, i64 400, i1 false)
-; CHECK-NEXT: br label [[CONT]]
-; CHECK: Cont:
-; CHECK-NEXT: [[A:%.*]] = phi i16 [ 514, [[F]] ], [ 257, [[T]] ]
-; CHECK-NEXT: ret i16 [[A]]
+; MDEP-LABEL: @memset_to_i16_nonlocal0(
+; MDEP-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
+; MDEP: T:
+; MDEP-NEXT: tail call void @llvm.memset.p0.i64(ptr [[P:%.*]], i8 1, i64 400, i1 false)
+; MDEP-NEXT: br label [[CONT:%.*]]
+; MDEP: F:
+; MDEP-NEXT: tail call void @llvm.memset.p0.i64(ptr [[P]], i8 2, i64 400, i1 false)
+; MDEP-NEXT: br label [[CONT]]
+; MDEP: Cont:
+; MDEP-NEXT: [[A:%.*]] = phi i16 [ 514, [[F]] ], [ 257, [[T]] ]
+; MDEP-NEXT: ret i16 [[A]]
+;
+; MSSA-LABEL: @memset_to_i16_nonlocal0(
+; MSSA-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
+; MSSA: T:
+; MSSA-NEXT: tail call void @llvm.memset.p0.i64(ptr [[P:%.*]], i8 1, i64 400, i1 false)
+; MSSA-NEXT: br label [[CONT:%.*]]
+; MSSA: F:
+; MSSA-NEXT: tail call void @llvm.memset.p0.i64(ptr [[P]], i8 2, i64 400, i1 false)
+; MSSA-NEXT: br label [[CONT]]
+; MSSA: Cont:
+; MSSA-NEXT: [[P2:%.*]] = getelementptr i16, ptr [[P]], i32 4
+; MSSA-NEXT: [[A:%.*]] = load i16, ptr [[P2]], align 2
+; MSSA-NEXT: ret i16 [[A]]
;
br i1 %cond, label %T, label %F
T:
@@ -251,10 +288,17 @@ Cont:
; memset -> float forwarding.
define float @memcpy_to_float_local(ptr %A) nounwind ssp {
-; CHECK-LABEL: @memcpy_to_float_local(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: tail call void @llvm.memcpy.p0.p0.i64(ptr [[A:%.*]], ptr @GCst, i64 12, i1 false)
-; CHECK-NEXT: ret float 1.400000e+01
+; MDEP-LABEL: @memcpy_to_float_local(
+; MDEP-NEXT: entry:
+; MDEP-NEXT: tail call void @llvm.memcpy.p0.p0.i64(ptr [[A:%.*]], ptr @GCst, i64 12, i1 false)
+; MDEP-NEXT: ret float 1.400000e+01
+;
+; MSSA-LABEL: @memcpy_to_float_local(
+; MSSA-NEXT: entry:
+; MSSA-NEXT: tail call void @llvm.memcpy.p0.p0.i64(ptr [[A:%.*]], ptr @GCst, i64 12, i1 false)
+; MSSA-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 1
+; MSSA-NEXT: [[TTMP2:%.*]] = load float, ptr [[ARRAYIDX]], align 4
+; MSSA-NEXT: ret float [[TTMP2]]
;
entry:
tail call void @llvm.memcpy.p0.p0.i64(ptr %A, ptr @GCst, i64 12, i1 false)
@@ -265,10 +309,17 @@ entry:
; memcpy from address space 1
define float @memcpy_to_float_local_as1(ptr %A) nounwind ssp {
-; CHECK-LABEL: @memcpy_to_float_local_as1(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: tail call void @llvm.memcpy.p0.p1.i64(ptr [[A:%.*]], ptr addrspace(1) @GCst_as1, i64 12, i1 false)
-; CHECK-NEXT: ret float 1.400000e+01
+; MDEP-LABEL: @memcpy_to_float_local_as1(
+; MDEP-NEXT: entry:
+; MDEP-NEXT: tail call void @llvm.memcpy.p0.p1.i64(ptr [[A:%.*]], ptr addrspace(1) @GCst_as1, i64 12, i1 false)
+; MDEP-NEXT: ret float 1.400000e+01
+;
+; MSSA-LABEL: @memcpy_to_float_local_as1(
+; MSSA-NEXT: entry:
+; MSSA-NEXT: tail call void @llvm.memcpy.p0.p1.i64(ptr [[A:%.*]], ptr addrspace(1) @GCst_as1, i64 12, i1 false)
+; MSSA-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 1
+; MSSA-NEXT: [[TTMP2:%.*]] = load float, ptr [[ARRAYIDX]], align 4
+; MSSA-NEXT: ret float [[TTMP2]]
;
entry:
tail call void @llvm.memcpy.p0.p1.i64(ptr %A, ptr addrspace(1) @GCst_as1, i64 12, i1 false)
@@ -279,29 +330,17 @@ entry:
;; non-local i32/float -> i8 load forwarding.
define i8 @coerce_mustalias_nonlocal0(ptr %P, i1 %cond) {
-; LE-LABEL: @coerce_mustalias_nonlocal0(
-; LE-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
-; LE: T:
-; LE-NEXT: store i32 42, ptr [[P:%.*]], align 4
-; LE-NEXT: br label [[CONT:%.*]]
-; LE: F:
-; LE-NEXT: store float 1.000000e+00, ptr [[P]], align 4
-; LE-NEXT: br label [[CONT]]
-; LE: Cont:
-; LE-NEXT: [[A:%.*]] = phi i8 [ 0, [[F]] ], [ 42, [[T]] ]
-; LE-NEXT: ret i8 [[A]]
-;
-; BE-LABEL: @coerce_mustalias_nonlocal0(
-; BE-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
-; BE: T:
-; BE-NEXT: store i32 42, ptr [[P:%.*]], align 4
-; BE-NEXT: br label [[CONT:%.*]]
-; BE: F:
-; BE-NEXT: store float 1.000000e+00, ptr [[P]], align 4
-; BE-NEXT: br label [[CONT]]
-; BE: Cont:
-; BE-NEXT: [[A:%.*]] = phi i8 [ 63, [[F]] ], [ 0, [[T]] ]
-; BE-NEXT: ret i8 [[A]]
+; MSSA-LABEL: @coerce_mustalias_nonlocal0(
+; MSSA-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
+; MSSA: T:
+; MSSA-NEXT: store i32 42, ptr [[P:%.*]], align 4
+; MSSA-NEXT: br label [[CONT:%.*]]
+; MSSA: F:
+; MSSA-NEXT: store float 1.000000e+00, ptr [[P]], align 4
+; MSSA-NEXT: br label [[CONT]]
+; MSSA: Cont:
+; MSSA-NEXT: [[A:%.*]] = load i8, ptr [[P]], align 1
+; MSSA-NEXT: ret i8 [[A]]
;
br i1 %cond, label %T, label %F
T:
@@ -322,29 +361,17 @@ Cont:
;; non-local i32/float -> i8 load forwarding. This also tests that the "P3"
;; bitcast equivalence can be properly phi translated.
define i8 @coerce_mustalias_nonlocal1(ptr %P, i1 %cond) {
-; LE-LABEL: @coerce_mustalias_nonlocal1(
-; LE-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
-; LE: T:
-; LE-NEXT: store i32 42, ptr [[P:%.*]], align 4
-; LE-NEXT: br label [[CONT:%.*]]
-; LE: F:
-; LE-NEXT: store float 1.000000e+00, ptr [[P]], align 4
-; LE-NEXT: br label [[CONT]]
-; LE: Cont:
-; LE-NEXT: [[A:%.*]] = phi i8 [ 0, [[F]] ], [ 42, [[T]] ]
-; LE-NEXT: ret i8 [[A]]
-;
-; BE-LABEL: @coerce_mustalias_nonlocal1(
-; BE-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
-; BE: T:
-; BE-NEXT: store i32 42, ptr [[P:%.*]], align 4
-; BE-NEXT: br label [[CONT:%.*]]
-; BE: F:
-; BE-NEXT: store float 1.000000e+00, ptr [[P]], align 4
-; BE-NEXT: br label [[CONT]]
-; BE: Cont:
-; BE-NEXT: [[A:%.*]] = phi i8 [ 63, [[F]] ], [ 0, [[T]] ]
-; BE-NEXT: ret i8 [[A]]
+; MSSA-LABEL: @coerce_mustalias_nonlocal1(
+; MSSA-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
+; MSSA: T:
+; MSSA-NEXT: store i32 42, ptr [[P:%.*]], align 4
+; MSSA-NEXT: br label [[CONT:%.*]]
+; MSSA: F:
+; MSSA-NEXT: store float 1.000000e+00, ptr [[P]], align 4
+; MSSA-NEXT: br label [[CONT]]
+; MSSA: Cont:
+; MSSA-NEXT: [[A:%.*]] = load i8, ptr [[P]], align 1
+; MSSA-NEXT: ret i8 [[A]]
;
br i1 %cond, label %T, label %F
T:
@@ -364,29 +391,16 @@ Cont:
;; non-local i32 -> i8 partial redundancy load forwarding.
define i8 @coerce_mustalias_pre0(ptr %P, i1 %cond) {
-; LE-LABEL: @coerce_mustalias_pre0(
-; LE-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
-; LE: T:
-; LE-NEXT: store i32 42, ptr [[P:%.*]], align 4
-; LE-NEXT: br label [[CONT:%.*]]
-; LE: F:
-; LE-NEXT: [[A_PRE:%.*]] = load i8, ptr [[P]], align 1
-; LE-NEXT: br label [[CONT]]
-; LE: Cont:
-; LE-NEXT: [[A:%.*]] = phi i8 [ [[A_PRE]], [[F]] ], [ 42, [[T]] ]
-; LE-NEXT: ret i8 [[A]]
-;
-; BE-LABEL: @coerce_mustalias_pre0(
-; BE-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
-; BE: T:
-; BE-NEXT: store i32 42, ptr [[P:%.*]], align 4
-; BE-NEXT: br label [[CONT:%.*]]
-; BE: F:
-; BE-NEXT: [[A_PRE:%.*]] = load i8, ptr [[P]], align 1
-; BE-NEXT: br label [[CONT]]
-; BE: Cont:
-; BE-NEXT: [[A:%.*]] = phi i8 [ [[A_PRE]], [[F]] ], [ 0, [[T]] ]
-; BE-NEXT: ret i8 [[A]]
+; MSSA-LABEL: @coerce_mustalias_pre0(
+; MSSA-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
+; MSSA: T:
+; MSSA-NEXT: store i32 42, ptr [[P:%.*]], align 4
+; MSSA-NEXT: br label [[CONT:%.*]]
+; MSSA: F:
+; MSSA-NEXT: br label [[CONT]]
+; MSSA: Cont:
+; MSSA-NEXT: [[A:%.*]] = load i8, ptr [[P]], align 1
+; MSSA-NEXT: ret i8 [[A]]
;
br i1 %cond, label %T, label %F
T:
@@ -410,17 +424,11 @@ Cont:
;; i32 -> i8 forwarding.
;; PR4216
define i8 @coerce_offset0(i32 %V, ptr %P) {
-; LE-LABEL: @coerce_offset0(
-; LE-NEXT: store i32 [[V:%.*]], ptr [[P:%.*]], align 4
-; LE-NEXT: [[TMP1:%.*]] = lshr i32 [[V]], 16
-; LE-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
-; LE-NEXT: ret i8 [[TMP2]]
-;
-; BE-LABEL: @coerce_offset0(
-; BE-NEXT: store i32 [[V:%.*]], ptr [[P:%.*]], align 4
-; BE-NEXT: [[TMP1:%.*]] = lshr i32 [[V]], 8
-; BE-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
-; BE-NEXT: ret i8 [[TMP2]]
+; MSSA-LABEL: @coerce_offset0(
+; MSSA-NEXT: store i32 [[V:%.*]], ptr [[P:%.*]], align 4
+; MSSA-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; MSSA-NEXT: [[A:%.*]] = load i8, ptr [[P3]], align 1
+; MSSA-NEXT: ret i8 [[A]]
;
store i32 %V, ptr %P
@@ -432,29 +440,18 @@ define i8 @coerce_offset0(i32 %V, ptr %P) {
;; non-local i32/float -> i8 load forwarding.
define i8 @coerce_offset_nonlocal0(ptr %P, i1 %cond) {
-; LE-LABEL: @coerce_offset_nonlocal0(
-; LE-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
-; LE: T:
-; LE-NEXT: store i32 57005, ptr [[P:%.*]], align 4
-; LE-NEXT: br label [[CONT:%.*]]
-; LE: F:
-; LE-NEXT: store float 1.000000e+00, ptr [[P]], align 4
-; LE-NEXT: br label [[CONT]]
-; LE: Cont:
-; LE-NEXT: [[A:%.*]] = phi i8 [ -128, [[F]] ], [ 0, [[T]] ]
-; LE-NEXT: ret i8 [[A]]
-;
-; BE-LABEL: @coerce_offset_nonlocal0(
-; BE-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
-; BE: T:
-; BE-NEXT: store i32 57005, ptr [[P:%.*]], align 4
-; BE-NEXT: br label [[CONT:%.*]]
-; BE: F:
-; BE-NEXT: store float 1.000000e+00, ptr [[P]], align 4
-; BE-NEXT: br label [[CONT]]
-; BE: Cont:
-; BE-NEXT: [[A:%.*]] = phi i8 [ 0, [[F]] ], [ -34, [[T]] ]
-; BE-NEXT: ret i8 [[A]]
+; MSSA-LABEL: @coerce_offset_nonlocal0(
+; MSSA-NEXT: [[P4:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
+; MSSA-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
+; MSSA: T:
+; MSSA-NEXT: store i32 57005, ptr [[P]], align 4
+; MSSA-NEXT: br label [[CONT:%.*]]
+; MSSA: F:
+; MSSA-NEXT: store float 1.000000e+00, ptr [[P]], align 4
+; MSSA-NEXT: br label [[CONT]]
+; MSSA: Cont:
+; MSSA-NEXT: [[A:%.*]] = load i8, ptr [[P4]], align 1
+; MSSA-NEXT: ret i8 [[A]]
;
%P4 = getelementptr i8, ptr %P, i32 2
br i1 %cond, label %T, label %F
@@ -475,18 +472,30 @@ Cont:
;; non-local i32 -> i8 partial redundancy load forwarding.
define i8 @coerce_offset_pre0(ptr %P, i1 %cond) {
-; CHECK-LABEL: @coerce_offset_pre0(
-; CHECK-NEXT: [[P4:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
-; CHECK-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
-; CHECK: T:
-; CHECK-NEXT: store i32 42, ptr [[P]], align 4
-; CHECK-NEXT: br label [[CONT:%.*]]
-; CHECK: F:
-; CHECK-NEXT: [[A_PRE:%.*]] = load i8, ptr [[P4]], align 1
-; CHECK-NEXT: br label [[CONT]]
-; CHECK: Cont:
-; CHECK-NEXT: [[A:%.*]] = phi i8 [ [[A_PRE]], [[F]] ], [ 0, [[T]] ]
-; CHECK-NEXT: ret i8 [[A]]
+; MDEP-LABEL: @coerce_offset_pre0(
+; MDEP-NEXT: [[P4:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
+; MDEP-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
+; MDEP: T:
+; MDEP-NEXT: store i32 42, ptr [[P]], align 4
+; MDEP-NEXT: br label [[CONT:%.*]]
+; MDEP: F:
+; MDEP-NEXT: [[A_PRE:%.*]] = load i8, ptr [[P4]], align 1
+; MDEP-NEXT: br label [[CONT]]
+; MDEP: Cont:
+; MDEP-NEXT: [[A:%.*]] = phi i8 [ [[A_PRE]], [[F]] ], [ 0, [[T]] ]
+; MDEP-NEXT: ret i8 [[A]]
+;
+; MSSA-LABEL: @coerce_offset_pre0(
+; MSSA-NEXT: [[P4:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
+; MSSA-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
+; MSSA: T:
+; MSSA-NEXT: store i32 42, ptr [[P]], align 4
+; MSSA-NEXT: br label [[CONT:%.*]]
+; MSSA: F:
+; MSSA-NEXT: br label [[CONT]]
+; MSSA: Cont:
+; MSSA-NEXT: [[A:%.*]] = load i8, ptr [[P4]], align 1
+; MSSA-NEXT: ret i8 [[A]]
;
%P4 = getelementptr i8, ptr %P, i32 2
br i1 %cond, label %T, label %F
@@ -504,20 +513,36 @@ Cont:
}
define i32 @chained_load(ptr %p, i32 %x, i32 %y) {
-; CHECK-LABEL: @chained_load(
-; CHECK-NEXT: block1:
-; CHECK-NEXT: [[A:%.*]] = alloca ptr, align 4
-; CHECK-NEXT: [[Z:%.*]] = load ptr, ptr [[P:%.*]], align 4
-; CHECK-NEXT: store ptr [[Z]], ptr [[A]], align 4
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: br i1 [[CMP]], label [[BLOCK2:%.*]], label [[BLOCK3:%.*]]
-; CHECK: block2:
-; CHECK-NEXT: br label [[BLOCK4:%.*]]
-; CHECK: block3:
-; CHECK-NEXT: br label [[BLOCK4]]
-; CHECK: block4:
-; CHECK-NEXT: [[D:%.*]] = load i32, ptr [[Z]], align 4
-; CHECK-NEXT: ret i32 [[D]]
+; MDEP-LABEL: @chained_load(
+; MDEP-NEXT: block1:
+; MDEP-NEXT: [[A:%.*]] = alloca ptr, align 4
+; MDEP-NEXT: [[Z:%.*]] = load ptr, ptr [[P:%.*]], align 4
+; MDEP-NEXT: store ptr [[Z]], ptr [[A]], align 4
+; MDEP-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], [[Y:%.*]]
+; MDEP-NEXT: br i1 [[CMP]], label [[BLOCK2:%.*]], label [[BLOCK3:%.*]]
+; MDEP: block2:
+; MDEP-NEXT: br label [[BLOCK4:%.*]]
+; MDEP: block3:
+; MDEP-NEXT: br label [[BLOCK4]]
+; MDEP: block4:
+; MDEP-NEXT: [[D:%.*]] = load i32, ptr [[Z]], align 4
+; MDEP-NEXT: ret i32 [[D]]
+;
+; MSSA-LABEL: @chained_load(
+; MSSA-NEXT: block1:
+; MSSA-NEXT: [[A:%.*]] = alloca ptr, align 4
+; MSSA-NEXT: [[Z:%.*]] = load ptr, ptr [[P:%.*]], align 4
+; MSSA-NEXT: store ptr [[Z]], ptr [[A]], align 4
+; MSSA-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], [[Y:%.*]]
+; MSSA-NEXT: br i1 [[CMP]], label [[BLOCK2:%.*]], label [[BLOCK3:%.*]]
+; MSSA: block2:
+; MSSA-NEXT: br label [[BLOCK4:%.*]]
+; MSSA: block3:
+; MSSA-NEXT: br label [[BLOCK4]]
+; MSSA: block4:
+; MSSA-NEXT: [[C:%.*]] = load ptr, ptr [[P]], align 4
+; MSSA-NEXT: [[D:%.*]] = load i32, ptr [[C]], align 4
+; MSSA-NEXT: ret i32 [[D]]
;
block1:
%A = alloca ptr
@@ -605,32 +630,62 @@ TY:
}
define i32 @phi_trans3(ptr %p, i32 %x, i32 %y, i32 %z) {
-; CHECK-LABEL: @phi_trans3(
-; CHECK-NEXT: block1:
-; CHECK-NEXT: [[CMPXY:%.*]] = icmp eq i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: br i1 [[CMPXY]], label [[BLOCK2:%.*]], label [[BLOCK3:%.*]]
-; CHECK: block2:
-; CHECK-NEXT: store i32 87, ptr [[P:%.*]], align 4
-; CHECK-NEXT: br label [[BLOCK4:%.*]]
-; CHECK: block3:
-; CHECK-NEXT: [[P2:%.*]] = getelementptr i32, ptr [[P]], i32 43
-; CHECK-NEXT: store i32 97, ptr [[P2]], align 4
-; CHECK-NEXT: br label [[BLOCK4]]
-; CHECK: block4:
-; CHECK-NEXT: [[D:%.*]] = phi i32 [ 87, [[BLOCK2]] ], [ 97, [[BLOCK3]] ]
-; CHECK-NEXT: br i1 [[CMPXY]], label [[BLOCK5:%.*]], label [[EXIT:%.*]]
-; CHECK: block5:
-; CHECK-NEXT: br i1 true, label [[BLOCK6:%.*]], label [[BLOCK5_EXIT_CRIT_EDGE:%.*]]
-; CHECK: block5.exit_crit_edge:
-; CHECK-NEXT: br label [[EXIT]]
-; CHECK: block6:
-; CHECK-NEXT: br i1 true, label [[BLOCK7:%.*]], label [[BLOCK6_EXIT_CRIT_EDGE:%.*]]
-; CHECK: block6.exit_crit_edge:
-; CHECK-NEXT: br label [[EXIT]]
-; CHECK: block7:
-; CHECK-NEXT: ret i32 [[D]]
-; CHECK: exit:
-; CHECK-NEXT: ret i32 -1
+; MDEP-LABEL: @phi_trans3(
+; MDEP-NEXT: block1:
+; MDEP-NEXT: [[CMPXY:%.*]] = icmp eq i32 [[X:%.*]], [[Y:%.*]]
+; MDEP-NEXT: br i1 [[CMPXY]], label [[BLOCK2:%.*]], label [[BLOCK3:%.*]]
+; MDEP: block2:
+; MDEP-NEXT: store i32 87, ptr [[P:%.*]], align 4
+; MDEP-NEXT: br label [[BLOCK4:%.*]]
+; MDEP: block3:
+; MDEP-NEXT: [[P2:%.*]] = getelementptr i32, ptr [[P]], i32 43
+; MDEP-NEXT: store i32 97, ptr [[P2]], align 4
+; MDEP-NEXT: br label [[BLOCK4]]
+; MDEP: block4:
+; MDEP-NEXT: [[D:%.*]] = phi i32 [ 87, [[BLOCK2]] ], [ 97, [[BLOCK3]] ]
+; MDEP-NEXT: br i1 [[CMPXY]], label [[BLOCK5:%.*]], label [[EXIT:%.*]]
+; MDEP: block5:
+; MDEP-NEXT: br i1 true, label [[BLOCK6:%.*]], label [[BLOCK5_EXIT_CRIT_EDGE:%.*]]
+; MDEP: block5.exit_crit_edge:
+; MDEP-NEXT: br label [[EXIT]]
+; MDEP: block6:
+; MDEP-NEXT: br i1 true, label [[BLOCK7:%.*]], label [[BLOCK6_EXIT_CRIT_EDGE:%.*]]
+; MDEP: block6.exit_crit_edge:
+; MDEP-NEXT: br label [[EXIT]]
+; MDEP: block7:
+; MDEP-NEXT: ret i32 [[D]]
+; MDEP: exit:
+; MDEP-NEXT: ret i32 -1
+;
+; MSSA-LABEL: @phi_trans3(
+; MSSA-NEXT: block1:
+; MSSA-NEXT: [[CMPXY:%.*]] = icmp eq i32 [[X:%.*]], [[Y:%.*]]
+; MSSA-NEXT: br i1 [[CMPXY]], label [[BLOCK2:%.*]], label [[BLOCK3:%.*]]
+; MSSA: block2:
+; MSSA-NEXT: store i32 87, ptr [[P:%.*]], align 4
+; MSSA-NEXT: br label [[BLOCK4:%.*]]
+; MSSA: block3:
+; MSSA-NEXT: [[P2:%.*]] = getelementptr i32, ptr [[P]], i32 43
+; MSSA-NEXT: store i32 97, ptr [[P2]], align 4
+; MSSA-NEXT: br label [[BLOCK4]]
+; MSSA: block4:
+; MSSA-NEXT: [[A:%.*]] = phi i32 [ -1, [[BLOCK2]] ], [ 42, [[BLOCK3]] ]
+; MSSA-NEXT: br i1 [[CMPXY]], label [[BLOCK5:%.*]], label [[EXIT:%.*]]
+; MSSA: block5:
+; MSSA-NEXT: [[B:%.*]] = add i32 [[A]], 1
+; MSSA-NEXT: br i1 true, label [[BLOCK6:%.*]], label [[BLOCK5_EXIT_CRIT_EDGE:%.*]]
+; MSSA: block5.exit_crit_edge:
+; MSSA-NEXT: br label [[EXIT]]
+; MSSA: block6:
+; MSSA-NEXT: [[C:%.*]] = getelementptr i32, ptr [[P]], i32 [[B]]
+; MSSA-NEXT: br i1 true, label [[BLOCK7:%.*]], label [[BLOCK6_EXIT_CRIT_EDGE:%.*]]
+; MSSA: block6.exit_crit_edge:
+; MSSA-NEXT: br label [[EXIT]]
+; MSSA: block7:
+; MSSA-NEXT: [[D:%.*]] = load i32, ptr [[C]], align 4
+; MSSA-NEXT: ret i32 [[D]]
+; MSSA: exit:
+; MSSA-NEXT: ret i32 -1
;
block1:
%cmpxy = icmp eq i32 %x, %y
@@ -668,21 +723,39 @@ exit:
}
define i8 @phi_trans4(ptr %p) {
-; CHECK-LABEL: @phi_trans4(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[X3:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 192
-; CHECK-NEXT: store i8 -64, ptr [[X3]], align 1
-; CHECK-NEXT: [[X:%.*]] = getelementptr i8, ptr [[P]], i32 4
-; CHECK-NEXT: [[Y2_PRE:%.*]] = load i8, ptr [[X]], align 1
-; CHECK-NEXT: br label [[LOOP:%.*]]
-; CHECK: loop:
-; CHECK-NEXT: [[Y2:%.*]] = phi i8 [ [[Y2_PRE]], [[ENTRY:%.*]] ], [ 0, [[LOOP]] ]
-; CHECK-NEXT: [[COND:%.*]] = call i1 @cond2()
-; CHECK-NEXT: store i32 0, ptr [[X3]], align 4
-; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[OUT:%.*]]
-; CHECK: out:
-; CHECK-NEXT: [[R:%.*]] = add i8 [[Y2_PRE]], [[Y2]]
-; CHECK-NEXT: ret i8 [[R]]
+; MDEP-LABEL: @phi_trans4(
+; MDEP-NEXT: entry:
+; MDEP-NEXT: [[X3:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 192
+; MDEP-NEXT: store i8 -64, ptr [[X3]], align 1
+; MDEP-NEXT: [[X:%.*]] = getelementptr i8, ptr [[P]], i32 4
+; MDEP-NEXT: [[Y:%.*]] = load i8, ptr [[X]], align 1
+; MDEP-NEXT: br label [[LOOP:%.*]]
+; MDEP: loop:
+; MDEP-NEXT: [[Y2:%.*]] = phi i8 [ [[Y]], [[ENTRY:%.*]] ], [ 0, [[LOOP]] ]
+; MDEP-NEXT: [[COND:%.*]] = call i1 @cond2()
+; MDEP-NEXT: store i32 0, ptr [[X3]], align 4
+; MDEP-NEXT: br i1 [[COND]], label [[LOOP]], label [[OUT:%.*]]
+; MDEP: out:
+; MDEP-NEXT: [[R:%.*]] = add i8 [[Y]], [[Y2]]
+; MDEP-NEXT: ret i8 [[R]]
+;
+; MSSA-LABEL: @phi_trans4(
+; MSSA-NEXT: entry:
+; MSSA-NEXT: [[X3:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 192
+; MSSA-NEXT: store i8 -64, ptr [[X3]], align 1
+; MSSA-NEXT: [[X:%.*]] = getelementptr i8, ptr [[P]], i32 4
+; MSSA-NEXT: [[Y:%.*]] = load i8, ptr [[X]], align 1
+; MSSA-NEXT: br label [[LOOP:%.*]]
+; MSSA: loop:
+; MSSA-NEXT: [[I:%.*]] = phi i32 [ 4, [[ENTRY:%.*]] ], [ 192, [[LOOP]] ]
+; MSSA-NEXT: [[X2:%.*]] = getelementptr i8, ptr [[P]], i32 [[I]]
+; MSSA-NEXT: [[Y2:%.*]] = load i8, ptr [[X2]], align 1
+; MSSA-NEXT: [[COND:%.*]] = call i1 @cond2()
+; MSSA-NEXT: store i32 0, ptr [[X3]], align 4
+; MSSA-NEXT: br i1 [[COND]], label [[LOOP]], label [[OUT:%.*]]
+; MSSA: out:
+; MSSA-NEXT: [[R:%.*]] = add i8 [[Y]], [[Y2]]
+; MSSA-NEXT: ret i8 [[R]]
;
entry:
%X3 = getelementptr i8, ptr %p, i32 192
@@ -709,28 +782,49 @@ out:
}
define i8 @phi_trans5(ptr %p) {
-; CHECK-LABEL: @phi_trans5(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[X4:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
-; CHECK-NEXT: store i8 19, ptr [[X4]], align 1
-; CHECK-NEXT: [[X:%.*]] = getelementptr i8, ptr [[P]], i32 4
-; CHECK-NEXT: [[Y:%.*]] = load i8, ptr [[X]], align 1
-; CHECK-NEXT: br label [[LOOP:%.*]]
-; CHECK: loop:
-; CHECK-NEXT: [[Y2:%.*]] = phi i8 [ [[Y]], [[ENTRY:%.*]] ], [ [[Y2_PRE:%.*]], [[CONT:%.*]] ]
-; CHECK-NEXT: [[I:%.*]] = phi i32 [ 4, [[ENTRY]] ], [ 3, [[CONT]] ]
-; CHECK-NEXT: [[X2:%.*]] = getelementptr i8, ptr [[P]], i32 [[I]]
-; CHECK-NEXT: [[COND:%.*]] = call i1 @cond2()
-; CHECK-NEXT: br i1 [[COND]], label [[CONT]], label [[OUT:%.*]]
-; CHECK: cont:
-; CHECK-NEXT: [[Z:%.*]] = getelementptr i8, ptr [[X2]], i32 -1
-; CHECK-NEXT: store i32 50462976, ptr [[Z]], align 4
-; CHECK-NEXT: [[X2_PHI_TRANS_INSERT:%.*]] = getelementptr i8, ptr [[P]], i32 3
-; CHECK-NEXT: [[Y2_PRE]] = load i8, ptr [[X2_PHI_TRANS_INSERT]], align 1
-; CHECK-NEXT: br label [[LOOP]]
-; CHECK: out:
-; CHECK-NEXT: [[R:%.*]] = add i8 [[Y]], [[Y2]]
-; CHECK-NEXT: ret i8 [[R]]
+; MDEP-LABEL: @phi_trans5(
+; MDEP-NEXT: entry:
+; MDEP-NEXT: [[X4:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
+; MDEP-NEXT: store i8 19, ptr [[X4]], align 1
+; MDEP-NEXT: [[X:%.*]] = getelementptr i8, ptr [[P]], i32 4
+; MDEP-NEXT: [[Y:%.*]] = load i8, ptr [[X]], align 1
+; MDEP-NEXT: br label [[LOOP:%.*]]
+; MDEP: loop:
+; MDEP-NEXT: [[Y2:%.*]] = phi i8 [ [[Y]], [[ENTRY:%.*]] ], [ [[Y2_PRE:%.*]], [[CONT:%.*]] ]
+; MDEP-NEXT: [[I:%.*]] = phi i32 [ 4, [[ENTRY]] ], [ 3, [[CONT]] ]
+; MDEP-NEXT: [[X2:%.*]] = getelementptr i8, ptr [[P]], i32 [[I]]
+; MDEP-NEXT: [[COND:%.*]] = call i1 @cond2()
+; MDEP-NEXT: br i1 [[COND]], label [[CONT]], label [[OUT:%.*]]
+; MDEP: cont:
+; MDEP-NEXT: [[Z:%.*]] = getelementptr i8, ptr [[X2]], i32 -1
+; MDEP-NEXT: store i32 50462976, ptr [[Z]], align 4
+; MDEP-NEXT: [[X2_PHI_TRANS_INSERT:%.*]] = getelementptr i8, ptr [[P]], i32 3
+; MDEP-NEXT: [[Y2_PRE]] = load i8, ptr [[X2_PHI_TRANS_INSERT]], align 1
+; MDEP-NEXT: br label [[LOOP]]
+; MDEP: out:
+; MDEP-NEXT: [[R:%.*]] = add i8 [[Y]], [[Y2]]
+; MDEP-NEXT: ret i8 [[R]]
+;
+; MSSA-LABEL: @phi_trans5(
+; MSSA-NEXT: entry:
+; MSSA-NEXT: [[X4:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
+; MSSA-NEXT: store i8 19, ptr [[X4]], align 1
+; MSSA-NEXT: [[X:%.*]] = getelementptr i8, ptr [[P]], i32 4
+; MSSA-NEXT: [[Y:%.*]] = load i8, ptr [[X]], align 1
+; MSSA-NEXT: br label [[LOOP:%.*]]
+; MSSA: loop:
+; MSSA-NEXT: [[I:%.*]] = phi i32 [ 4, [[ENTRY:%.*]] ], [ 3, [[CONT:%.*]] ]
+; MSSA-NEXT: [[X2:%.*]] = getelementptr i8, ptr [[P]], i32 [[I]]
+; MSSA-NEXT: [[Y2:%.*]] = load i8, ptr [[X2]], align 1
+; MSSA-NEXT: [[COND:%.*]] = call i1 @cond2()
+; MSSA-NEXT: br i1 [[COND]], label [[CONT]], label [[OUT:%.*]]
+; MSSA: cont:
+; MSSA-NEXT: [[Z:%.*]] = getelementptr i8, ptr [[X2]], i32 -1
+; MSSA-NEXT: store i32 50462976, ptr [[Z]], align 4
+; MSSA-NEXT: br label [[LOOP]]
+; MSSA: out:
+; MSSA-NEXT: [[R:%.*]] = add i8 [[Y]], [[Y2]]
+; MSSA-NEXT: ret i8 [[R]]
;
entry:
@@ -766,24 +860,40 @@ declare void @use_i32(i32) readonly
; into header. Make sure we translate the address for %l1 correctly where
; parts of the address computations are in different basic blocks.
define i32 @phi_trans6(ptr noalias nocapture readonly %x, i1 %cond) {
-; CHECK-LABEL: @phi_trans6(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[L0:%.*]] = load i32, ptr [[X:%.*]], align 4
-; CHECK-NEXT: call void @use_i32(i32 [[L0]])
-; CHECK-NEXT: br label [[HEADER:%.*]]
-; CHECK: header:
-; CHECK-NEXT: [[L1_PRE:%.*]] = phi i32 [ [[L0]], [[ENTRY:%.*]] ], [ [[L1_PRE1:%.*]], [[LATCH_HEADER_CRIT_EDGE:%.*]] ]
-; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[IV_NEXT:%.*]], [[LATCH_HEADER_CRIT_EDGE]] ]
-; CHECK-NEXT: indirectbr ptr blockaddress(@phi_trans6, [[LATCH:%.*]]), [label %latch]
-; CHECK: latch:
-; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
-; CHECK-NEXT: br i1 [[COND:%.*]], label [[EXIT:%.*]], label [[LATCH_HEADER_CRIT_EDGE]]
-; CHECK: latch.header_crit_edge:
-; CHECK-NEXT: [[GEP_1_PHI_TRANS_INSERT_PHI_TRANS_INSERT:%.*]] = getelementptr i32, ptr [[X]], i32 [[IV_NEXT]]
-; CHECK-NEXT: [[L1_PRE1]] = load i32, ptr [[GEP_1_PHI_TRANS_INSERT_PHI_TRANS_INSERT]], align 4
-; CHECK-NEXT: br label [[HEADER]]
-; CHECK: exit:
-; CHECK-NEXT: ret i32 [[L1_PRE]]
+; MDEP-LABEL: @phi_trans6(
+; MDEP-NEXT: entry:
+; MDEP-NEXT: [[L0:%.*]] = load i32, ptr [[X:%.*]], align 4
+; MDEP-NEXT: call void @use_i32(i32 [[L0]])
+; MDEP-NEXT: br label [[HEADER:%.*]]
+; MDEP: header:
+; MDEP-NEXT: [[L1:%.*]] = phi i32 [ [[L0]], [[ENTRY:%.*]] ], [ [[L1_PRE:%.*]], [[LATCH_HEADER_CRIT_EDGE:%.*]] ]
+; MDEP-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[IV_NEXT:%.*]], [[LATCH_HEADER_CRIT_EDGE]] ]
+; MDEP-NEXT: indirectbr ptr blockaddress(@phi_trans6, [[LATCH:%.*]]), [label %latch]
+; MDEP: latch:
+; MDEP-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; MDEP-NEXT: br i1 [[COND:%.*]], label [[EXIT:%.*]], label [[LATCH_HEADER_CRIT_EDGE]]
+; MDEP: latch.header_crit_edge:
+; MDEP-NEXT: [[GEP_1_PHI_TRANS_INSERT_PHI_TRANS_INSERT:%.*]] = getelementptr i32, ptr [[X]], i32 [[IV_NEXT]]
+; MDEP-NEXT: [[L1_PRE]] = load i32, ptr [[GEP_1_PHI_TRANS_INSERT_PHI_TRANS_INSERT]], align 4
+; MDEP-NEXT: br label [[HEADER]]
+; MDEP: exit:
+; MDEP-NEXT: ret i32 [[L1]]
+;
+; MSSA-LABEL: @phi_trans6(
+; MSSA-NEXT: entry:
+; MSSA-NEXT: [[L0:%.*]] = load i32, ptr [[X:%.*]], align 4
+; MSSA-NEXT: call void @use_i32(i32 [[L0]])
+; MSSA-NEXT: br label [[HEADER:%.*]]
+; MSSA: header:
+; MSSA-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
+; MSSA-NEXT: indirectbr ptr blockaddress(@phi_trans6, [[LATCH]]), [label %latch]
+; MSSA: latch:
+; MSSA-NEXT: [[GEP_1:%.*]] = getelementptr i32, ptr [[X]], i32 [[IV]]
+; MSSA-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_1]], align 4
+; MSSA-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; MSSA-NEXT: br i1 [[COND:%.*]], label [[EXIT:%.*]], label [[HEADER]]
+; MSSA: exit:
+; MSSA-NEXT: ret i32 [[L1]]
;
entry:
%l0 = load i32, ptr %x
@@ -806,24 +916,41 @@ exit:
; FIXME: Currently we fail to translate the PHI in this case.
define i32 @phi_trans7(ptr noalias nocapture readonly %x, i1 %cond) {
-; CHECK-LABEL: @phi_trans7(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[L0:%.*]] = load i32, ptr [[X:%.*]], align 4
-; CHECK-NEXT: call void @use_i32(i32 [[L0]])
-; CHECK-NEXT: br label [[HEADER:%.*]]
-; CHECK: header:
-; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 2, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH_HEADER_CRIT_EDGE:%.*]] ]
-; CHECK-NEXT: [[OFFSET:%.*]] = add i32 [[IV]], -2
-; CHECK-NEXT: indirectbr ptr blockaddress(@phi_trans7, [[LATCH:%.*]]), [label %latch]
-; CHECK: latch:
-; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr i32, ptr [[X]], i32 [[OFFSET]]
-; CHECK-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_1]], align 4
-; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
-; CHECK-NEXT: br i1 [[COND:%.*]], label [[EXIT:%.*]], label [[LATCH_HEADER_CRIT_EDGE]]
-; CHECK: latch.header_crit_edge:
-; CHECK-NEXT: br label [[HEADER]]
-; CHECK: exit:
-; CHECK-NEXT: ret i32 [[L1]]
+; MDEP-LABEL: @phi_trans7(
+; MDEP-NEXT: entry:
+; MDEP-NEXT: [[L0:%.*]] = load i32, ptr [[X:%.*]], align 4
+; MDEP-NEXT: call void @use_i32(i32 [[L0]])
+; MDEP-NEXT: br label [[HEADER:%.*]]
+; MDEP: header:
+; MDEP-NEXT: [[IV:%.*]] = phi i32 [ 2, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH_HEADER_CRIT_EDGE:%.*]] ]
+; MDEP-NEXT: [[OFFSET:%.*]] = add i32 [[IV]], -2
+; MDEP-NEXT: indirectbr ptr blockaddress(@phi_trans7, [[LATCH:%.*]]), [label %latch]
+; MDEP: latch:
+; MDEP-NEXT: [[GEP_1:%.*]] = getelementptr i32, ptr [[X]], i32 [[OFFSET]]
+; MDEP-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_1]], align 4
+; MDEP-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; MDEP-NEXT: br i1 [[COND:%.*]], label [[EXIT:%.*]], label [[LATCH_HEADER_CRIT_EDGE]]
+; MDEP: latch.header_crit_edge:
+; MDEP-NEXT: br label [[HEADER]]
+; MDEP: exit:
+; MDEP-NEXT: ret i32 [[L1]]
+;
+; MSSA-LABEL: @phi_trans7(
+; MSSA-NEXT: entry:
+; MSSA-NEXT: [[L0:%.*]] = load i32, ptr [[X:%.*]], align 4
+; MSSA-NEXT: call void @use_i32(i32 [[L0]])
+; MSSA-NEXT: br label [[HEADER:%.*]]
+; MSSA: header:
+; MSSA-NEXT: [[IV:%.*]] = phi i32 [ 2, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
+; MSSA-NEXT: [[OFFSET:%.*]] = add i32 [[IV]], -2
+; MSSA-NEXT: indirectbr ptr blockaddress(@phi_trans7, [[LATCH]]), [label %latch]
+; MSSA: latch:
+; MSSA-NEXT: [[GEP_1:%.*]] = getelementptr i32, ptr [[X]], i32 [[OFFSET]]
+; MSSA-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_1]], align 4
+; MSSA-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; MSSA-NEXT: br i1 [[COND:%.*]], label [[EXIT:%.*]], label [[HEADER]]
+; MSSA: exit:
+; MSSA-NEXT: ret i32 [[L1]]
;
entry:
%l0 = load i32, ptr %x
@@ -847,24 +974,41 @@ exit:
; FIXME: Currently we fail to translate the PHI in this case.
define i32 @phi_trans8(ptr noalias nocapture readonly %x, i1 %cond) {
-; CHECK-LABEL: @phi_trans8(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[L0:%.*]] = load i32, ptr [[X:%.*]], align 4
-; CHECK-NEXT: call void @use_i32(i32 [[L0]])
-; CHECK-NEXT: br label [[HEADER:%.*]]
-; CHECK: header:
-; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 2, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH_HEADER_CRIT_EDGE:%.*]] ]
-; CHECK-NEXT: indirectbr ptr blockaddress(@phi_trans8, [[LATCH:%.*]]), [label %latch]
-; CHECK: latch:
-; CHECK-NEXT: [[OFFSET:%.*]] = add i32 [[IV]], -2
-; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr i32, ptr [[X]], i32 [[OFFSET]]
-; CHECK-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_1]], align 4
-; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
-; CHECK-NEXT: br i1 [[COND:%.*]], label [[EXIT:%.*]], label [[LATCH_HEADER_CRIT_EDGE]]
-; CHECK: latch.header_crit_edge:
-; CHECK-NEXT: br label [[HEADER]]
-; CHECK: exit:
-; CHECK-NEXT: ret i32 [[L1]]
+; MDEP-LABEL: @phi_trans8(
+; MDEP-NEXT: entry:
+; MDEP-NEXT: [[L0:%.*]] = load i32, ptr [[X:%.*]], align 4
+; MDEP-NEXT: call void @use_i32(i32 [[L0]])
+; MDEP-NEXT: br label [[HEADER:%.*]]
+; MDEP: header:
+; MDEP-NEXT: [[IV:%.*]] = phi i32 [ 2, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH_HEADER_CRIT_EDGE:%.*]] ]
+; MDEP-NEXT: indirectbr ptr blockaddress(@phi_trans8, [[LATCH:%.*]]), [label %latch]
+; MDEP: latch:
+; MDEP-NEXT: [[OFFSET:%.*]] = add i32 [[IV]], -2
+; MDEP-NEXT: [[GEP_1:%.*]] = getelementptr i32, ptr [[X]], i32 [[OFFSET]]
+; MDEP-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_1]], align 4
+; MDEP-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; MDEP-NEXT: br i1 [[COND:%.*]], label [[EXIT:%.*]], label [[LATCH_HEADER_CRIT_EDGE]]
+; MDEP: latch.header_crit_edge:
+; MDEP-NEXT: br label [[HEADER]]
+; MDEP: exit:
+; MDEP-NEXT: ret i32 [[L1]]
+;
+; MSSA-LABEL: @phi_trans8(
+; MSSA-NEXT: entry:
+; MSSA-NEXT: [[L0:%.*]] = load i32, ptr [[X:%.*]], align 4
+; MSSA-NEXT: call void @use_i32(i32 [[L0]])
+; MSSA-NEXT: br label [[HEADER:%.*]]
+; MSSA: header:
+; MSSA-NEXT: [[IV:%.*]] = phi i32 [ 2, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
+; MSSA-NEXT: indirectbr ptr blockaddress(@phi_trans8, [[LATCH]]), [label %latch]
+; MSSA: latch:
+; MSSA-NEXT: [[OFFSET:%.*]] = add i32 [[IV]], -2
+; MSSA-NEXT: [[GEP_1:%.*]] = getelementptr i32, ptr [[X]], i32 [[OFFSET]]
+; MSSA-NEXT: [[L1:%.*]] = load i32, ptr [[GEP_1]], align 4
+; MSSA-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; MSSA-NEXT: br i1 [[COND:%.*]], label [[EXIT:%.*]], label [[HEADER]]
+; MSSA: exit:
+; MSSA-NEXT: ret i32 [[L1]]
;
entry:
%l0 = load i32, ptr %x
@@ -890,11 +1034,18 @@ exit:
; PR6642
define i32 @memset_to_load() nounwind readnone {
-; CHECK-LABEL: @memset_to_load(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[X:%.*]] = alloca [256 x i32], align 4
-; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[X]], i8 0, i64 1024, i1 false)
-; CHECK-NEXT: ret i32 0
+; MDEP-LABEL: @memset_to_load(
+; MDEP-NEXT: entry:
+; MDEP-NEXT: [[X:%.*]] = alloca [256 x i32], align 4
+; MDEP-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[X]], i8 0, i64 1024, i1 false)
+; MDEP-NEXT: ret i32 0
+;
+; MSSA-LABEL: @memset_to_load(
+; MSSA-NEXT: entry:
+; MSSA-NEXT: [[X:%.*]] = alloca [256 x i32], align 4
+; MSSA-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[X]], i8 0, i64 1024, i1 false)
+; MSSA-NEXT: [[TTMP1:%.*]] = load i32, ptr [[X]], align 4
+; MSSA-NEXT: ret i32 [[TTMP1]]
;
entry:
%x = alloca [256 x i32], align 4 ; <ptr> [#uses=2]
@@ -910,23 +1061,14 @@ entry:
;;===----------------------------------------------------------------------===;;
define i32 @load_load_partial_alias(ptr %P) nounwind ssp {
-; LE-LABEL: @load_load_partial_alias(
-; LE-NEXT: entry:
-; LE-NEXT: [[TTMP2:%.*]] = load i32, ptr [[P:%.*]], align 4
-; LE-NEXT: [[TMP0:%.*]] = lshr i32 [[TTMP2]], 8
-; LE-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
-; LE-NEXT: [[CONV:%.*]] = zext i8 [[TMP1]] to i32
-; LE-NEXT: [[ADD:%.*]] = add nsw i32 [[TTMP2]], [[CONV]]
-; LE-NEXT: ret i32 [[ADD]]
-;
-; BE-LABEL: @load_load_partial_alias(
-; BE-NEXT: entry:
-; BE-NEXT: [[TTMP2:%.*]] = load i32, ptr [[P:%.*]], align 4
-; BE-NEXT: [[TMP0:%.*]] = lshr i32 [[TTMP2]], 16
-; BE-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
-; BE-NEXT: [[CONV:%.*]] = zext i8 [[TMP1]] to i32
-; BE-NEXT: [[ADD:%.*]] = add nsw i32 [[TTMP2]], [[CONV]]
-; BE-NEXT: ret i32 [[ADD]]
+; MSSA-LABEL: @load_load_partial_alias(
+; MSSA-NEXT: entry:
+; MSSA-NEXT: [[TTMP2:%.*]] = load i32, ptr [[P:%.*]], align 4
+; MSSA-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 1
+; MSSA-NEXT: [[TTMP5:%.*]] = load i8, ptr [[ADD_PTR]], align 1
+; MSSA-NEXT: [[CONV:%.*]] = zext i8 [[TTMP5]] to i32
+; MSSA-NEXT: [[ADD:%.*]] = add nsw i32 [[TTMP2]], [[CONV]]
+; MSSA-NEXT: ret i32 [[ADD]]
;
entry:
%ttmp2 = load i32, ptr %P
@@ -940,31 +1082,18 @@ entry:
; Cross block partial alias case.
define i32 @load_load_partial_alias_cross_block(ptr %P) nounwind ssp {
-; LE-LABEL: @load_load_partial_alias_cross_block(
-; LE-NEXT: entry:
-; LE-NEXT: [[X1:%.*]] = load i32, ptr [[P:%.*]], align 4
-; LE-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
-; LE-NEXT: [[TMP0:%.*]] = lshr i32 [[X1]], 8
-; LE-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
-; LE-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[IF_END:%.*]]
-; LE: land.lhs.true:
-; LE-NEXT: [[CONV6:%.*]] = zext i8 [[TMP1]] to i32
-; LE-NEXT: ret i32 [[CONV6]]
-; LE: if.end:
-; LE-NEXT: ret i32 52
-;
-; BE-LABEL: @load_load_partial_alias_cross_block(
-; BE-NEXT: entry:
-; BE-NEXT: [[X1:%.*]] = load i32, ptr [[P:%.*]], align 4
-; BE-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
-; BE-NEXT: [[TMP0:%.*]] = lshr i32 [[X1]], 16
-; BE-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
-; BE-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[IF_END:%.*]]
-; BE: land.lhs.true:
-; BE-NEXT: [[CONV6:%.*]] = zext i8 [[TMP1]] to i32
-; BE-NEXT: ret i32 [[CONV6]]
-; BE: if.end:
-; BE-NEXT: ret i32 52
+; MSSA-LABEL: @load_load_partial_alias_cross_block(
+; MSSA-NEXT: entry:
+; MSSA-NEXT: [[X1:%.*]] = load i32, ptr [[P:%.*]], align 4
+; MSSA-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
+; MSSA-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[IF_END:%.*]]
+; MSSA: land.lhs.true:
+; MSSA-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 1
+; MSSA-NEXT: [[TTMP5:%.*]] = load i8, ptr [[ARRAYIDX4]], align 1
+; MSSA-NEXT: [[CONV6:%.*]] = zext i8 [[TTMP5]] to i32
+; MSSA-NEXT: ret i32 [[CONV6]]
+; MSSA: if.end:
+; MSSA-NEXT: ret i32 52
;
entry:
%x1 = load i32, ptr %P, align 4
@@ -982,45 +1111,23 @@ if.end:
}
define i32 @load_load_partial_alias_cross_block_phi_trans(ptr %P) nounwind {
-; LE-LABEL: @load_load_partial_alias_cross_block_phi_trans(
-; LE-NEXT: entry:
-; LE-NEXT: [[X1:%.*]] = load i32, ptr [[P:%.*]], align 4
-; LE-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
-; LE-NEXT: [[TMP0:%.*]] = lshr i32 [[X1]], 16
-; LE-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
-; LE-NEXT: [[TMP2:%.*]] = lshr i32 [[X1]], 8
-; LE-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
-; LE-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[ELSE:%.*]]
-; LE: if:
-; LE-NEXT: br label [[JOIN:%.*]]
-; LE: else:
-; LE-NEXT: br label [[JOIN]]
-; LE: join:
-; LE-NEXT: [[TTMP5:%.*]] = phi i8 [ [[TMP3]], [[IF]] ], [ [[TMP1]], [[ELSE]] ]
-; LE-NEXT: [[CONV6:%.*]] = zext i8 [[TTMP5]] to i32
-; LE-NEXT: ret i32 [[CONV6]]
-; LE: if.end:
-; LE-NEXT: ret i32 52
-;
-; BE-LABEL: @load_load_partial_alias_cross_block_phi_trans(
-; BE-NEXT: entry:
-; BE-NEXT: [[X1:%.*]] = load i32, ptr [[P:%.*]], align 4
-; BE-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
-; BE-NEXT: [[TMP0:%.*]] = lshr i32 [[X1]], 8
-; BE-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
-; BE-NEXT: [[TMP2:%.*]] = lshr i32 [[X1]], 16
-; BE-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
-; BE-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[ELSE:%.*]]
-; BE: if:
-; BE-NEXT: br label [[JOIN:%.*]]
-; BE: else:
-; BE-NEXT: br label [[JOIN]]
-; BE: join:
-; BE-NEXT: [[TTMP5:%.*]] = phi i8 [ [[TMP3]], [[IF]] ], [ [[TMP1]], [[ELSE]] ]
-; BE-NEXT: [[CONV6:%.*]] = zext i8 [[TTMP5]] to i32
-; BE-NEXT: ret i32 [[CONV6]]
-; BE: if.end:
-; BE-NEXT: ret i32 52
+; MSSA-LABEL: @load_load_partial_alias_cross_block_phi_trans(
+; MSSA-NEXT: entry:
+; MSSA-NEXT: [[X1:%.*]] = load i32, ptr [[P:%.*]], align 4
+; MSSA-NEXT: [[CMP:%.*]] = icmp eq i32 [[X1]], 127
+; MSSA-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[ELSE:%.*]]
+; MSSA: if:
+; MSSA-NEXT: br label [[JOIN:%.*]]
+; MSSA: else:
+; MSSA-NEXT: br label [[JOIN]]
+; MSSA: join:
+; MSSA-NEXT: [[IDX:%.*]] = phi i64 [ 1, [[IF]] ], [ 2, [[ELSE]] ]
+; MSSA-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 [[IDX]]
+; MSSA-NEXT: [[TTMP5:%.*]] = load i8, ptr [[ARRAYIDX4]], align 1
+; MSSA-NEXT: [[CONV6:%.*]] = zext i8 [[TTMP5]] to i32
+; MSSA-NEXT: ret i32 [[CONV6]]
+; MSSA: if.end:
+; MSSA-NEXT: ret i32 52
;
entry:
%x1 = load i32, ptr %P, align 4
@@ -1047,58 +1154,26 @@ if.end:
}
define void @load_load_partial_alias_loop(ptr %P) {
-; LE-LABEL: @load_load_partial_alias_loop(
-; LE-NEXT: entry:
-; LE-NEXT: [[P_1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1
-; LE-NEXT: [[V_1:%.*]] = load i8, ptr [[P_1]], align 1
-; LE-NEXT: call void @use.i8(i8 [[V_1]])
-; LE-NEXT: [[V_1_32:%.*]] = load i32, ptr [[P_1]], align 4
-; LE-NEXT: call void @use.i32(i32 [[V_1_32]])
-; LE-NEXT: [[TMP0:%.*]] = trunc i32 [[V_1_32]] to i8
-; LE-NEXT: br label [[LOOP:%.*]]
-; LE: loop:
-; LE-NEXT: [[V_I:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[TMP2:%.*]], [[LOOP_LOOP_CRIT_EDGE:%.*]] ]
-; LE-NEXT: [[I:%.*]] = phi i64 [ 1, [[ENTRY]] ], [ [[I_INC:%.*]], [[LOOP_LOOP_CRIT_EDGE]] ]
-; LE-NEXT: [[P_I:%.*]] = getelementptr i8, ptr [[P]], i64 [[I]]
-; LE-NEXT: call void @use.i8(i8 [[V_I]])
-; LE-NEXT: [[V_I_32:%.*]] = load i32, ptr [[P_I]], align 4
-; LE-NEXT: call void @use.i32(i32 [[V_I_32]])
-; LE-NEXT: [[I_INC]] = add i64 [[I]], 1
-; LE-NEXT: [[CMP:%.*]] = icmp ne i64 [[I_INC]], 64
-; LE-NEXT: [[TMP1:%.*]] = lshr i32 [[V_I_32]], 8
-; LE-NEXT: [[TMP2]] = trunc i32 [[TMP1]] to i8
-; LE-NEXT: br i1 [[CMP]], label [[LOOP_LOOP_CRIT_EDGE]], label [[EXIT:%.*]]
-; LE: loop.loop_crit_edge:
-; LE-NEXT: br label [[LOOP]]
-; LE: exit:
-; LE-NEXT: ret void
-;
-; BE-LABEL: @load_load_partial_alias_loop(
-; BE-NEXT: entry:
-; BE-NEXT: [[P_1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1
-; BE-NEXT: [[V_1:%.*]] = load i8, ptr [[P_1]], align 1
-; BE-NEXT: call void @use.i8(i8 [[V_1]])
-; BE-NEXT: [[V_1_32:%.*]] = load i32, ptr [[P_1]], align 4
-; BE-NEXT: call void @use.i32(i32 [[V_1_32]])
-; BE-NEXT: [[TMP0:%.*]] = lshr i32 [[V_1_32]], 24
-; BE-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
-; BE-NEXT: br label [[LOOP:%.*]]
-; BE: loop:
-; BE-NEXT: [[V_I:%.*]] = phi i8 [ [[TMP1]], [[ENTRY:%.*]] ], [ [[TMP3:%.*]], [[LOOP_LOOP_CRIT_EDGE:%.*]] ]
-; BE-NEXT: [[I:%.*]] = phi i64 [ 1, [[ENTRY]] ], [ [[I_INC:%.*]], [[LOOP_LOOP_CRIT_EDGE]] ]
-; BE-NEXT: [[P_I:%.*]] = getelementptr i8, ptr [[P]], i64 [[I]]
-; BE-NEXT: call void @use.i8(i8 [[V_I]])
-; BE-NEXT: [[V_I_32:%.*]] = load i32, ptr [[P_I]], align 4
-; BE-NEXT: call void @use.i32(i32 [[V_I_32]])
-; BE-NEXT: [[I_INC]] = add i64 [[I]], 1
-; BE-NEXT: [[CMP:%.*]] = icmp ne i64 [[I_INC]], 64
-; BE-NEXT: [[TMP2:%.*]] = lshr i32 [[V_I_32]], 16
-; BE-NEXT: [[TMP3]] = trunc i32 [[TMP2]] to i8
-; BE-NEXT: br i1 [[CMP]], label [[LOOP_LOOP_CRIT_EDGE]], label [[EXIT:%.*]]
-; BE: loop.loop_crit_edge:
-; BE-NEXT: br label [[LOOP]]
-; BE: exit:
-; BE-NEXT: ret void
+; MSSA-LABEL: @load_load_partial_alias_loop(
+; MSSA-NEXT: entry:
+; MSSA-NEXT: [[P_1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1
+; MSSA-NEXT: [[V_1:%.*]] = load i8, ptr [[P_1]], align 1
+; MSSA-NEXT: call void @use.i8(i8 [[V_1]])
+; MSSA-NEXT: [[V_1_32:%.*]] = load i32, ptr [[P_1]], align 4
+; MSSA-NEXT: call void @use.i32(i32 [[V_1_32]])
+; MSSA-NEXT: br label [[LOOP:%.*]]
+; MSSA: loop:
+; MSSA-NEXT: [[I:%.*]] = phi i64 [ 1, [[ENTRY:%.*]] ], [ [[I_INC:%.*]], [[LOOP]] ]
+; MSSA-NEXT: [[P_I:%.*]] = getelementptr i8, ptr [[P]], i64 [[I]]
+; MSSA-NEXT: [[V_I:%.*]] = load i8, ptr [[P_I]], align 1
+; MSSA-NEXT: call void @use.i8(i8 [[V_I]])
+; MSSA-NEXT: [[V_I_32:%.*]] = load i32, ptr [[P_I]], align 4
+; MSSA-NEXT: call void @use.i32(i32 [[V_I_32]])
+; MSSA-NEXT: [[I_INC]] = add i64 [[I]], 1
+; MSSA-NEXT: [[CMP:%.*]] = icmp ne i64 [[I_INC]], 64
+; MSSA-NEXT: br i1 [[CMP]], label [[LOOP]], label [[EXIT:%.*]]
+; MSSA: exit:
+; MSSA-NEXT: ret void
;
entry:
%P.1 = getelementptr i8, ptr %P, i64 1
@@ -1129,37 +1204,16 @@ declare void @use.i32(i32) readnone
@global = external local_unnamed_addr global i8, align 4
define void @load_load_partial_alias_atomic(ptr %arg) {
-; LE-LABEL: @load_load_partial_alias_atomic(
-; LE-NEXT: bb:
-; LE-NEXT: [[TMP2_1:%.*]] = getelementptr inbounds i8, ptr [[ARG:%.*]], i64 1
-; LE-NEXT: [[TMP2_3:%.*]] = load i64, ptr [[TMP2_1]], align 4
-; LE-NEXT: [[TMP3_1:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 2
-; LE-NEXT: [[TMP0:%.*]] = lshr i64 [[TMP2_3]], 8
-; LE-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i8
-; LE-NEXT: br label [[BB5:%.*]]
-; LE: bb5:
-; LE-NEXT: [[TMP4_1:%.*]] = phi i8 [ [[TMP4_1_PRE:%.*]], [[BB5]] ], [ [[TMP1]], [[BB:%.*]] ]
-; LE-NEXT: [[TMP6_1:%.*]] = load atomic i8, ptr @global acquire, align 4
-; LE-NEXT: [[TMP7_1:%.*]] = add i8 [[TMP6_1]], [[TMP4_1]]
-; LE-NEXT: store i8 [[TMP7_1]], ptr [[ARG]], align 1
-; LE-NEXT: [[TMP4_1_PRE]] = load i8, ptr [[TMP3_1]], align 4
-; LE-NEXT: br label [[BB5]]
-;
-; BE-LABEL: @load_load_partial_alias_atomic(
-; BE-NEXT: bb:
-; BE-NEXT: [[TMP2_1:%.*]] = getelementptr inbounds i8, ptr [[ARG:%.*]], i64 1
-; BE-NEXT: [[TMP2_3:%.*]] = load i64, ptr [[TMP2_1]], align 4
-; BE-NEXT: [[TMP3_1:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 2
-; BE-NEXT: [[TMP0:%.*]] = lshr i64 [[TMP2_3]], 48
-; BE-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i8
-; BE-NEXT: br label [[BB5:%.*]]
-; BE: bb5:
-; BE-NEXT: [[TMP4_1:%.*]] = phi i8 [ [[TMP4_1_PRE:%.*]], [[BB5]] ], [ [[TMP1]], [[BB:%.*]] ]
-; BE-NEXT: [[TMP6_1:%.*]] = load atomic i8, ptr @global acquire, align 4
-; BE-NEXT: [[TMP7_1:%.*]] = add i8 [[TMP6_1]], [[TMP4_1]]
-; BE-NEXT: store i8 [[TMP7_1]], ptr [[ARG]], align 1
-; BE-NEXT: [[TMP4_1_PRE]] = load i8, ptr [[TMP3_1]], align 4
-; BE-NEXT: br label [[BB5]]
+; MSSA-LABEL: @load_load_partial_alias_atomic(
+; MSSA-NEXT: bb:
+; MSSA-NEXT: [[TMP3_1:%.*]] = getelementptr inbounds i8, ptr [[ARG:%.*]], i64 2
+; MSSA-NEXT: br label [[BB5:%.*]]
+; MSSA: bb5:
+; MSSA-NEXT: [[TMP4_1:%.*]] = load i8, ptr [[TMP3_1]], align 4
+; MSSA-NEXT: [[TMP6_1:%.*]] = load atomic i8, ptr @global acquire, align 4
+; MSSA-NEXT: [[TMP7_1:%.*]] = add i8 [[TMP6_1]], [[TMP4_1]]
+; MSSA-NEXT: store i8 [[TMP7_1]], ptr [[ARG]], align 1
+; MSSA-NEXT: br label [[BB5]]
;
bb:
%tmp2.1 = getelementptr inbounds i8, ptr %arg, i64 1
@@ -1262,12 +1316,20 @@ declare void @use3(ptr, ptr)
; PR8908
define void @test_escape1() nounwind {
-; CHECK-LABEL: @test_escape1(
-; CHECK-NEXT: [[X:%.*]] = alloca ptr, align 8
-; CHECK-NEXT: store ptr getelementptr inbounds ([5 x ptr], ptr @_ZTV1X, i64 0, i64 2), ptr [[X]], align 8
-; CHECK-NEXT: call void @use() #[[ATTR3]]
-; CHECK-NEXT: call void @use3(ptr [[X]], ptr getelementptr inbounds ([5 x ptr], ptr @_ZTV1X, i64 0, i64 2)) #[[ATTR3]]
-; CHECK-NEXT: ret void
+; MDEP-LABEL: @test_escape1(
+; MDEP-NEXT: [[X:%.*]] = alloca ptr, align 8
+; MDEP-NEXT: store ptr getelementptr inbounds ([5 x ptr], ptr @_ZTV1X, i64 0, i64 2), ptr [[X]], align 8
+; MDEP-NEXT: call void @use() #[[ATTR3]]
+; MDEP-NEXT: call void @use3(ptr [[X]], ptr getelementptr inbounds ([5 x ptr], ptr @_ZTV1X, i64 0, i64 2)) #[[ATTR3]]
+; MDEP-NEXT: ret void
+;
+; MSSA-LABEL: @test_escape1(
+; MSSA-NEXT: [[X:%.*]] = alloca ptr, align 8
+; MSSA-NEXT: store ptr getelementptr inbounds ([5 x ptr], ptr @_ZTV1X, i64 0, i64 2), ptr [[X]], align 8
+; MSSA-NEXT: call void @use() #[[ATTR3]]
+; MSSA-NEXT: [[DEAD:%.*]] = load ptr, ptr [[X]], align 8
+; MSSA-NEXT: call void @use3(ptr [[X]], ptr [[DEAD]]) #[[ATTR3]]
+; MSSA-NEXT: ret void
;
%x = alloca ptr, align 8
store ptr getelementptr inbounds ([5 x ptr], ptr @_ZTV1X, i64 0, i64 2), ptr %x, align 8
@@ -1276,3 +1338,6 @@ define void @test_escape1() nounwind {
call void @use3(ptr %x, ptr %DEAD) nounwind
ret void
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; BE: {{.*}}
+; LE: {{.*}}
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